Abstract: A frequency mixer circuit includes a gain stage and a mixer. The gain stage has a specific circuit design to convert a differential input voltage signal into a differential current signal with an input frequency. The mixer receives a differential local oscillator (LO) voltage signal with a LO frequency, and the differential current signal from the gain stage, and outputs a differential output voltage signal having a mixed frequency associated with the input frequency and the LO frequency.

Abstract: A frequency mixer circuit includes a mixer, a load stage, and again stage. The load stage cooperates with the mixer to generate a differential output voltage signal with a mixed frequency according to a differential local oscillator voltage signal and a differential input voltage signal. The gain stage has a transconductance, and a magnitude of the differential current signal and the transconductance have a positive relationship therebetween, so as to result in a positive relationship between the transconductance and a conversion gain which is a ratio of magnitude of the differential output voltage signal to magnitude of the differential input voltage signal.

Abstract: An apparatus includes a spiral conductor, a first electronic device, and a second electronic device. The spiral conductor has first and second ends. The first end is a first port of the conductor. An intermediate portion of the conductor is a second port of the conductor. The second end is a third port of the conductor. The first electronic device has a first terminal connected to the first port and has a second terminal connected to the second port. The first electronic device is capable of carrying a current between the first and second terminals. The second electronic device has a third terminal that operates as a current source or sink. The third terminal is connected to the third port.

Abstract: Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. The method is particularly useful within the context of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrications.

Abstract: Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. The method is particularly useful within the context of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrications.

Abstract: An array of DRAM cells having Y-shaped multi-fin stacked capacitors with increased capacitance is achieved. A planar first insulating layer is formed over the semi-conductor devices on the substrate. Polycide bit lines are formed on the first insulating layer, and a second insulating layer and a silicon nitride (Si.sub.3 N.sub.4) etch-stop layer are conformally deposited. A multilayer, composed of a alternating insulating and polysilicon layers, is conformally deposited over the bit lines. Capacitor node contact openings are etched in the multilayer and in the underlying layers to the substrate. A fourth polysilicon layer is deposited sufficiently thick to fill the node contact openings and to form the node contacts. The multilayer is then patterned to leave portions over the node contacts, and an isotropic etch is used to remove the insulating layers exposed in the sidewalls of the patterned multilayer to provide Y-shaped multi-fin capacitor bottom electrodes over the bit lines.