Patents by Inventor Yohei Sawada

Yohei Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200232873
    Abstract: An abnormality detection method performed using a flow rate control device including a restriction portion, a control valve, a first pressure sensor, a second pressure sensor, and a downstream valve, includes a step of changing the control valve and the downstream valve from an open state to a closed state, a step of measuring an upstream pressure or a downstream pressure in the closed state, and at least one step of (a) extracting an upstream pressure at a point when a difference between the upstream pressure and the downstream pressure reaches a predetermined value as an upstream convergence pressure, and extracting the downstream pressure as a downstream convergence pressure, and (b) extracting the time from a point when the control valve are changed to a closed state to a point when a difference between the upstream pressure and the downstream pressure reaches a predetermined value as a convergence time.
    Type: Application
    Filed: December 15, 2016
    Publication date: July 23, 2020
    Applicant: FUJIKIN INCORPORATED
    Inventors: Masaaki NAGASE, Kaoru HIRATA, Yohei SAWADA, Kouji NISHINO, Nobukazu IKEDA
  • Patent number: 10706917
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Yuichiro Ishii, Yohei Sawada, Makoto Yabuuchi
  • Patent number: 10665430
    Abstract: A gas supply system includes: a first flow channel connecting a first gas source and a chamber; a second flow channel connecting a second gas source and the first flow channel; a control valve, provided in the second flow channel, configured to control a flow rate of the second gas; an orifice provided downstream of the control valve and at a terminus of the second flow channel; a switching valve, provided at a connection point between the first flow channel and the terminus of the second flow channel, configured to control a supply timing of the second gas; an exhaust mechanism, connected to a flow channel between the control valve and the orifice in the second flow channel, configured to exhaust the second gas; and a controller configured to bring the control valve, the switching valve and the exhaust mechanism into operation.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 26, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Atsushi Sawachi, Norihiko Amikura, Kouji Nishino, Yohei Sawada, Yoshiharu Kishida
  • Publication number: 20200159257
    Abstract: A fluid control system (1) comprises: a first valve (21) provided downstream of a flow rate controller (10), a flow rate measuring device (30) provided downstream of the first valve (21) and having a second valve (22), an open/close detector (26) provided to the second valve (22), and a controller (25) for controlling an open/close operation of the first valve (21) and the second valve (22), and the controller (25) controls the open/close operation of the first valve (21) in response to a signal output from the open/close detector (26).
    Type: Application
    Filed: July 24, 2018
    Publication date: May 21, 2020
    Applicant: FUJIKIN INCORPORATED
    Inventors: Satoru YAMASHITA, Yohei SAWADA, Masaaki NAGASE, Kouji NISHINO, Nobukazu IKEDA
  • Patent number: 10648572
    Abstract: A valve with a built-in orifice includes a base section having a housing recess and first and second flow passages; a valve seat body; an inner disc; a valve element; and an orifice body, wherein the housing recess has a wide-diameter section and a narrow-diameter section, the first flow passage is connected to a space between a wall surface of the narrow-diameter section and the orifice body to communicate with a valve chamber, and the second flow passage communicates with the valve chamber through a through hole of the orifice body and a through hole of the valve seat body.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 12, 2020
    Assignee: FUJIKIN INCORPORATED
    Inventors: Yohei Sawada, Kaoru Hirata, Masaaki Nagase, Kouji Nishino, Nobukazu Ikeda
  • Publication number: 20200127458
    Abstract: In a power storage system, a three-phase AC wire is connected to a three-phase AC power system. Power storage blocks, each of which includes a power storage module and a power conditioner, are connected in parallel to the three-phase AC wire. A system controller individually controls power storage blocks. The power storage modules each includes: a power storage unit; and a management unit that manages the power storage unit. The power conditioner includes a power converter and a controller. The power converter converts DC power discharged into single-phase AC power and outputs the converted AC power to two lines of the three-phase AC wire, or converts single-phase AC power received from the two lines of the three-phase AC wire into DC power and charges the power storage unit. The controller is connected to the system controller via a communication line and the management unit via a communication line.
    Type: Application
    Filed: April 16, 2018
    Publication date: April 23, 2020
    Inventors: MASAKI KATO, NAOHISA MORIMOTO, MASAAKI KURANUKI, JUN YAMASAKI, YOHEI ISHII, KOICHI SAWADA
  • Patent number: 10629264
    Abstract: A content addressable memory includes a plurality of TCAM cells which configure one entry, a first word line coupled to the TCAM cells, a second word line coupled to the TCAM cells and a match line coupled to the TCAM cells and further includes a valid cell which stores a valid bit which indicates validity or invalidity of the entry, a bit line coupled to the valid line and a selection circuit which is coupled to the first word line and the second word line and sets the valid cell to a selected state in accordance with a situation where the first word line or the second word line is set to the selected state.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yohei Sawada, Makoto Yabuuchi, Masao Morimoto
  • Publication number: 20200011720
    Abstract: The flow rate measuring method is performed in a common gas supply system comprising a plurality of gas supply paths each having a first valve, and a gas measuring device formed downstream side of the plurality of gas supply paths, having a pressure sensor, a temperature sensor, and a downstream side second valve.
    Type: Application
    Filed: February 8, 2018
    Publication date: January 9, 2020
    Applicant: FUJIKIN INCORPORATED
    Inventors: Masaaki NAGASE, Yohei SAWADA, Kouji NISHINO, Nobukazu IKEDA
  • Patent number: 10453519
    Abstract: A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 22, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yohei Sawada, Makoto Yabuuchi, Yuichiro Ishii
  • Publication number: 20190317337
    Abstract: There is provided a contact lens having a convex front surface and a concave rear surface, the front surface being divided into an optical portion, an edge joining the front and rear surfaces, a first smoothing portion arranged on an outer periphery of the optical portion, a peripheral portion arranged on an outer periphery of the first smoothing portion, and a second smoothing portion connecting the peripheral portion and the edge, the front surface having mirror image symmetry with respect to a vertical meridian as a boundary extending from an upper end of the lens to a lower end of the lens passing through a midpoint of the lens, and having mirror image symmetry also with respect to the horizontal meridian perpendicular to the vertical meridian at the lens midpoint, the peripheral portion being arranged to include the horizontal meridian, and configured of: a first peripheral portion arranged to include the horizontal meridian and having a shape so as to maximize a thickness of the contact lens on the hori
    Type: Application
    Filed: November 25, 2016
    Publication date: October 17, 2019
    Applicant: HOYA CORPORATION
    Inventors: Yohei SAWADA, Takaharu NAKAJIMA, Naoki TSUJI
  • Publication number: 20190304699
    Abstract: In a multilayer capacitor, a multilayer capacitor main body includes first and second main surfaces, first and second side surfaces, and first and second end surfaces, the first and second main surfaces extending in a length direction and a width direction, the first and second side surfaces extending in the length direction and a thickness direction, and the first and second end surfaces extending in the width direction and the thickness direction. The second main surface is depressed in a portion extending from opposite ends of the second main surface toward a center of the second main surface in the length direction.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Inventors: Sui UNO, Takashi SAWADA, Yohei MUKOBATA
  • Publication number: 20190212176
    Abstract: A substrate processing system includes a gas supply unit having a first gas flow channel. A second gas flow channel of a flow rate measurement system is connected to the first gas flow channel. The flow rate measurement system further includes a third gas flow channel connected to the second gas flow channel, and a pressure sensor and a temperature sensor that measure a pressure and a temperature, respectively, in the third gas flow channel. In a method of an embodiment, a flow rate of a gas output from a flow rate controller of the gas supply unit is calculated using a build-up method. The flow rate of a gas is calculated without using the total volume of the first gas flow channel and the second gas flow channel and temperatures in the first gas flow channel and the second gas flow channel.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 11, 2019
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Risako MIYOSHI, Norihiko AMIKURA, Kazuyuki MIURA, Masaaki NAGASE, Satoru YAMASHITA, Yohei SAWADA, Kouji NISHINO, Nobukazu IKEDA
  • Patent number: 10340085
    Abstract: In a multilayer capacitor, a multilayer capacitor main body includes first and second main surfaces, first and second side surfaces, and first and second end surfaces, the first and second main surfaces extending in a length direction and a width direction, the first and second side surfaces extending in the length direction and a thickness direction, and the first and second end surfaces extending in the width direction and the thickness direction. The second main surface is depressed in a portion extending from opposite ends of the second main surface toward a center of the second main surface in the length direction.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 2, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Sui Uno, Takashi Sawada, Yohei Mukobata
  • Publication number: 20190189197
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 20, 2019
    Inventors: Koji NII, Yuichiro ISHII, Yohei SAWADA, Makoto YABUUCHI
  • Publication number: 20190178389
    Abstract: A valve with a built-in orifice includes a base section having a housing recess and first and second flow passages; a valve seat body; an inner disc; a valve element; and an orifice body, wherein the housing recess has a wide-diameter section and a narrow-diameter section, the first flow passage is connected to a space between a wall surface of the narrow-diameter section and the orifice body to communicate with a valve chamber, and the second flow passage communicates with the valve chamber through a through hole of the orifice body and a through hole of the valve seat body.
    Type: Application
    Filed: July 25, 2017
    Publication date: June 13, 2019
    Applicant: FUJIKIN INCORPORATED
    Inventors: Yohei SAWADA, Kaoru HIRATA, Masaaki NAGASE, Kouji NISHINO, Nobukazu IKEDA
  • Publication number: 20190165192
    Abstract: The present invention pertains to a light absorption layer for forming a solar cell and a photoelectric conversion element having excellent durability and photoelectric conversion efficiency in the near infrared region, and a solar cell and a photoelectric conversion element having the light absorption layer. This light absorption layer contains a perovskite compound having a band gap energy of 1.7-4.0 eV, and a quantum dot having a band gap energy equal to or higher than 0.2 eV and equal to or lower than the band gap energy of the perovskite compound.
    Type: Application
    Filed: March 30, 2017
    Publication date: May 30, 2019
    Applicant: KAO CORPORATION
    Inventors: Hiroji HOSOKAWA, Takuya SAWADA, Yohei SHIRAISHI
  • Publication number: 20190137309
    Abstract: In a method of calibrating a flow rate control device in which a flow rate is calibrated based on comparison with a flow rate measured by a flow rate reference gauge, a predetermined permissible error range is set for a plurality of flow rate settings, and the permissible error range of at least one specific flow rate setting among the plurality of flow rate settings is set to be smaller than the predetermined permissible error range.
    Type: Application
    Filed: June 22, 2017
    Publication date: May 9, 2019
    Applicant: FUJIKIN INCORPORATED
    Inventors: Yohei SAWADA, Masaaki NAGASE, Kouji NISHINO, Nobukazu IKEDA
  • Publication number: 20190129452
    Abstract: The fluid controller includes a fluid control module and an external control module. The fluid control module includes a control valve on a flow channel, a valve driver circuit that drives the control valve, a fluid meter on a flow channel, and a first processor that processes a signal output from the fluid meter. The external control module includes a second processor that processes a signal output from the first processor. The second processor outputs a valve control signal according to the signal of the fluid meter output from the first processor, the valve control signal is directly input to the valve driver circuit without through the first processor, and the valve driver circuit outputs a voltage that drives the control valve according to the valve control signal from the second processor.
    Type: Application
    Filed: April 21, 2017
    Publication date: May 2, 2019
    Applicant: FUJIKIN INCORPORATED
    Inventors: Kaoru HIRATA, Katsuyuki SUGITA, Yohei SAWADA, Masahiko TAKIMOTO, Kouji NISHINO
  • Publication number: 20190094847
    Abstract: A pressure-type flow rate control device includes a restriction part, a control valve disposed upstream of the restriction part, an upstream pressure sensor, a downstream pressure sensor, and a controller that diagnoses flow rate control by using pressure drop data on a flow passage between the control valve and the restriction part and reference pressure drop data, wherein a close command is issued to the control valve and a shutoff valve provided downstream of the downstream pressure sensor, and the controller determines whether a predetermined critical expansion condition is satisfied by using outputs of the upstream pressure sensor and the downstream pressure sensor after the control valve is closed, and diagnoses flow rate control by using the pressure drop data acquired during a period in which the predetermined critical expansion condition is satisfied.
    Type: Application
    Filed: March 23, 2017
    Publication date: March 28, 2019
    Applicant: FUJIKIN INCORPORATED
    Inventors: Masaaki NAGASE, Kaoru HIRATA, Yohei SAWADA, Katsuyuki SUGITA, Kouji NISHINO, Nobukazu IKEDA
  • Publication number: 20190027212
    Abstract: A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.
    Type: Application
    Filed: September 27, 2018
    Publication date: January 24, 2019
    Inventors: Yohei SAWADA, Makoto YABUUCHI, Yuichiro ISHII