Patents by Inventor Yoichi Nogami

Yoichi Nogami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8519440
    Abstract: A semiconductor device includes: a semiconductor substrate of a compound semiconductor material; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The carrier density in the channel layer varies with distance from a top surface of the channel layer and is inversely proportional to the third power of depth into the channel layer from the top surface of the channel layer. The buffer layer has a lower electron affinity than the channel layer and is a different compound semiconductor material from the channel layer.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: August 27, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoichi Nogami
  • Publication number: 20120217557
    Abstract: A semiconductor device includes: a semiconductor substrate of a compound semiconductor material; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The carrier density in the channel layer varies with distance from a top surface of the channel layer and is inversely proportional to the third power of depth into the channel layer from the top surface of the channel layer. The buffer layer has a lower electron affinity than the channel layer and is a different compound semiconductor material from the channel layer.
    Type: Application
    Filed: May 1, 2012
    Publication date: August 30, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Yoichi NOGAMI
  • Patent number: 8193566
    Abstract: A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The dopant impurity concentration in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer. The gate electrode has a gate length in a range from 0.2 ?m to 0.6 ?m.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: June 5, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoichi Nogami
  • Publication number: 20120007153
    Abstract: A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The dopant impurity concentration in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer. The gate electrode has a gate length in a range from 0.2 ?m to 0.6 ?m.
    Type: Application
    Filed: September 21, 2011
    Publication date: January 12, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Yoichi NOGAMI
  • Patent number: 8039871
    Abstract: A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially formed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being a compound semiconductor; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The dopant impurity concentration profile in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer. The channel layer has fixed sheet dopant impurity concentration, and the top surface of the channel layer has a dopant concentration in a range from 5.0×1017 cm?3 to 2.0×1018 cm?3.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 18, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoichi Nogami
  • Patent number: 7622767
    Abstract: In a semiconductor device, a SiN first protective insulating film is formed on a semiconductor layer. A T-shaped gate electrode is formed on the semiconductor layer. A SiN second protective insulating film spreads in an umbrella shape from above the T-shaped gate electrode. A hollow region is formed between the two SiN films. The SiN films are coated with a SiN third protective insulating film with the hollow region remaining.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: November 24, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichi Nogami, Toshikazu Hirayama
  • Publication number: 20090014758
    Abstract: In a semiconductor device, a SiN first protective insulating film is formed on a semiconductor layer. A T-shaped gate electrode is formed on the semiconductor layer. A SiN second protective insulating film spreads in an umbrella shape from above the T-shaped gate electrode. A hollow region is formed between the two SiN films. The SiN films are coated with a SiN third protective insulating film with the hollow region remaining.
    Type: Application
    Filed: November 21, 2007
    Publication date: January 15, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoichi Nogami, Toshikazu Hirayama
  • Publication number: 20080283882
    Abstract: A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially formed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being a compound semiconductor; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The carrier density in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer, the channel layer has a uniform sheet carrier density, and the top surface of the channel layer has a dopant concentration in a range from 5.0×1017 cm?3 to 2.0×1018 cm?3.
    Type: Application
    Filed: October 30, 2007
    Publication date: November 20, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Yoichi Nogami
  • Patent number: 7442644
    Abstract: To remove the disparate substrate from nitride semiconductor layer grown over the disparate substrate, that is made of a material different from nitride semiconductor, by irradiating the disparate substrate with laser beam having a wavelength shorter than the band gap wavelength of the nitride semiconductor layer, while supplying an acidic or alkaline etching solution to the interface between the disparate substrate and the nitride semiconductor layer.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: October 28, 2008
    Assignee: Nichia Corporation
    Inventor: Yoichi Nogami
  • Publication number: 20080122060
    Abstract: A semiconductor device packaged in a non-hermetic package includes a semiconductor substrate; a wiring metal film on the semiconductor substrate; a plating power supply film on the wiring metal film; an Au plated portion on the plating power supply film; a metal film covering the Au plated portion; and an insulating protective film covering the metal film. The metal film is a material having corrosion resistance properties such that a potential-pH diagram of the metal material predominantly includes a corrosion-free region and a passive region and either does not include a corrosion region or includes a very small corrosion region, the potential-pH diagram showing the effects of electrical potential and pH on corrosion of the metal material.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 29, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoichi NOGAMI, Koichi FUJITA
  • Publication number: 20060189017
    Abstract: To remove the disparate substrate from nitride semiconductor layer grown over the disparate substrate, that is made of a material different from nitride semiconductor, by irradiating the disparate substrate with laser beam having a wavelength shorter than the band gap wavelength of the nitride semiconductor layer, while supplying an acidic or alkaline etching solution to the interface between the disparate substrate and the nitride semiconductor layer.
    Type: Application
    Filed: July 20, 2005
    Publication date: August 24, 2006
    Applicant: NICHIA CORPORATION
    Inventor: Yoichi Nogami
  • Patent number: 4202393
    Abstract: Disclosed is a run flat tire for motorcycles having a high handling stability, cornering stability and durability even when the tire is punctured during running and the pneumatic pressure inside of the tire becomes equal to atmospheric pressure. The run flat tire has a pair of sidewall-reinforcing layers each comprising (1) an elastic filler extending from an end location adjacent a bead core in a bead portion to the other end location in a tread portion through a sidewall portion of the tire and (2) at least one reinforcing ply which extends along one side surface of the elastic filler toward the tread portion, is turned up around the end of the elastic filler in the tread portion and which then further extends along the other side surface of the elastic filler toward the bead portion.
    Type: Grant
    Filed: July 26, 1978
    Date of Patent: May 13, 1980
    Assignee: The Yokohama Rubber Co., Ltd.
    Inventors: Ryo Ikeda, Yoichi Nogami, Teruo Koizumi