Patents by Inventor Yoichi Tamaki
Yoichi Tamaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7837431Abstract: In an impeller 11, an inlet portion and an outlet portion are provided at one end side and the other end side in the axial direction, respectively. An inlet 29 is formed in the lower part of the inlet portion, and an outlet is formed in the side face of the outlet portion. The inlet portion and the outlet portion are partitioned by a flange portion 40. The impeller 11 includes a primary vane 36 and a secondary vane 38. The primary vane 36 defines a spiral primary channel 35 that connects the inlet 29 and the outlet. The secondary vane 38 is formed in a shape that a part of the outer periphery of the outlet portion is gouged inward so as to define a secondary channel 37 connected to the primary channel 35 and extending circumferentially around the outer periphery.Type: GrantFiled: June 30, 2004Date of Patent: November 23, 2010Assignee: Shinmaywa Industries, Ltd.Inventors: Yasuyuki Nishi, Chikara Takebe, Koichi Tamura, Yoichi Tamaki, Akihiro Ando, Arata Funasaka
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Patent number: 7576406Abstract: A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.Type: GrantFiled: February 9, 2004Date of Patent: August 18, 2009Assignee: Hitachi, Ltd.Inventors: Yoichi Tamaki, Hideaki Nonami, Masato Hamamoto
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Patent number: 7238582Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: December 1, 2004Date of Patent: July 3, 2007Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 7089525Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.Type: GrantFiled: October 21, 2003Date of Patent: August 8, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
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Publication number: 20050101097Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: ApplicationFiled: December 1, 2004Publication date: May 12, 2005Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 6876067Abstract: A semiconductor device improved in reliability is disclosed. The semiconductor device comprises a semiconductor chip, a sealing member which seals the semiconductor chip with resin, a tub having a chip bonding surface for bonding with the chip and a back surface located on the side opposite to the chip bonding surface and exposed to a surface of the sealing member, plural inner leads electrically connected respectively to bonding pads on the semiconductor chip through wires such as gold wires, and plural outer leads integrally connected respectively to the inner leads and projecting to the exterior of the sealing member, wherein surfaces of the tub and the plural inner and outer leads are all coated with palladium plating.Type: GrantFiled: March 26, 2003Date of Patent: April 5, 2005Assignee: Hitachi, Ltd.Inventors: Taiga Arai, Fujiaki Nose, Hiroshi Kikuchi, Yoichi Tamaki
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Publication number: 20050013688Abstract: In an impeller 11, an inlet portion and an outlet portion are provided at one end side and the other end side in the axial direction, respectively. An inlet 29 is formed in the lower part of the inlet portion, and an outlet is formed in the side face of the outlet portion. The inlet portion and the outlet portion are partitioned by a flange portion 40. The impeller 11 includes a primary vane 36 and a secondary vane 38. The primary vane 36 defines a spiral primary channel 35 that connects the inlet 29 and the outlet. The secondary vane 38 is formed in a shape that a part of the outer periphery of the outlet portion is gouged inward so as to define a secondary channel 37 connected to the primary channel 35 and extending circumferentially around the outer periphery.Type: ApplicationFiled: June 30, 2004Publication date: January 20, 2005Applicant: ShinMaywa Industries, Ltd.Inventors: Yasuyuki Nishi, Chikara Takebe, Koichi Tamura, Yoichi Tamaki, Akihiro Ando, Arata Funasaka
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Patent number: 6835632Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: June 13, 2003Date of Patent: December 28, 2004Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Publication number: 20040183159Abstract: A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.Type: ApplicationFiled: February 9, 2004Publication date: September 23, 2004Applicant: Hitachi, Ltd.Inventors: Yoichi Tamaki, Hideaki Nonami, Masato Hamamoto
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Publication number: 20040079996Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.Type: ApplicationFiled: October 21, 2003Publication date: April 29, 2004Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
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Patent number: 6662344Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.Type: GrantFiled: March 8, 2002Date of Patent: December 9, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
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Publication number: 20030222281Abstract: A semiconductor device improved in reliability is disclosed. The semiconductor device comprises a semiconductor chip, a sealing member which seals the semiconductor chip with resin, a tub having a chip bonding surface for bonding with the chip and a back surface located on the side opposite to the chip bonding surface and exposed to a surface of the sealing member, plural inner leads electrically connected respectively to bonding pads on the semiconductor chip through wires such as gold wires, and plural outer leads integrally connected respectively to the inner leads and projecting to the exterior of the sealing member, wherein surfaces of the tub and the plural inner and outer leads are all coated with palladium plating.Type: ApplicationFiled: March 26, 2003Publication date: December 4, 2003Applicant: Hitachi, Ltd.Inventors: Taiga Arai, Fujiaki Nose, Hiroshi Kikuchi, Yoichi Tamaki
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Publication number: 20030207544Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: ApplicationFiled: June 13, 2003Publication date: November 6, 2003Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 6610569Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: August 28, 2000Date of Patent: August 26, 2003Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 6573578Abstract: A photo semiconductor integrated circuit device has a photodiode portion and amplifier portion, each portion having a buried layer. The impurity concentration and/or depth of the buried layer for the photodiode portion is lower than that of the buried layer for the amplifier portion. As a result, the frequency band width is widened.Type: GrantFiled: August 6, 2001Date of Patent: June 3, 2003Assignee: Hitachi, Ltd.Inventors: Shigeharu Kimura, Kenji Maio, Takeshi Doi, Yoichi Tamaki, Takeshi Shimano
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Patent number: 6524924Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: July 28, 1998Date of Patent: February 25, 2003Assignees: Hitachi, Ltd., Hitachi Device EngineeringInventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Publication number: 20020149084Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.Type: ApplicationFiled: March 8, 2002Publication date: October 17, 2002Applicant: Hitachi, Ltd.Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
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Publication number: 20020070417Abstract: Disclosed is an optical information processor having high-speed reading property by improving responsivity and extension of the frequency band width of a photodiode prepared on one identical substrate together with other semiconductor integrated circuit device. To extend the frequency band width, a buried layer of a photodiode portion is deeply implanted or the impurity concentration of the buried layer is lowered. To improve the responsivity, the thickness of the oxide layer of the SOI substrate is selected such that the reflected light is maximized.Type: ApplicationFiled: August 6, 2001Publication date: June 13, 2002Inventors: Shigeharu Kimura, Kenji Maio, Takeshi Doi, Yoichi Tamaki, Takeshi Shimano
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Patent number: 6133094Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: July 28, 1998Date of Patent: October 17, 2000Assignees: Hitachi Ltd, Hitachi Device Engineering Co.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 5846869Abstract: A method of manufacturing a bipolar transistor having an improved polysilicon emitter is disclosed. More specifically, hydrogen terminations or OH group terminations adhered (bonded) to an emitter-forming region are eliminated by a heat treatment in an inert gas atmosphere before forming emitter polysilicon. Subsequently, an amorphous silicon film for forming an emitter polysilicon is formed at a low temperature.Type: GrantFiled: July 24, 1996Date of Patent: December 8, 1998Assignee: Hitachi, Ltd.Inventors: Takashi Hashimoto, Hideo Miura, Toshiyuki Kikuchi, Toshiyuki Mine, Yoichi Tamaki, Takahiro Kumauchi