Patents by Inventor Yoichi Tamaki

Yoichi Tamaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200176652
    Abstract: A light emitting device includes: a light emitting element; a wavelength conversion member disposed on or above an upper surface of the light emitting element; a light-transmissive member disposed on an upper surface of the wavelength conversion member; and a light reflective member disposed on each side surface of the light emitting element, the wavelength conversion member, and the light-transmissive member, wherein an upper surface of the light reflective member is coplanar with an upper surface of the light-transmissive member, and wherein each of the upper surface of the light reflective member and the upper surface of the light-transmissive member is a cut surface.
    Type: Application
    Filed: February 7, 2020
    Publication date: June 4, 2020
    Applicant: NICHIA CORPORATION
    Inventors: Suguru BEPPU, Yoichi BANDO, Hiroto TAMAKI, Takuya NAKABAYASHI
  • Patent number: 10600942
    Abstract: A light emitting device includes a semiconductor light emitting element; and a light reflective member having a multilayer structure and covering the side faces of the semiconductor light emitting element. The light reflective member includes: a first layer disposed on an inner, semiconductor light emitting element side, the first layer comprising a light-transmissive resin containing a light reflective substance, and a second layer disposed in contact with an outer side of the first layer, the second layer comprising a light-transmissive resin containing the light reflective substance at a lower content than that of the first layer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 24, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Suguru Beppu, Yoichi Bando, Hiroto Tamaki, Takuya Nakabayashi
  • Publication number: 20190140152
    Abstract: A light emitting device includes a semiconductor light emitting element; and a light reflective member having a multilayer structure and covering the side faces of the semiconductor light emitting element. The light reflective member includes: a first layer disposed on an inner, semiconductor light emitting element side, the first layer comprising a light-transmissive resin containing a light reflective substance, and a second layer disposed in contact with an outer side of the first layer, the second layer comprising a light-transmissive resin containing the light reflective substance at a lower content than that of the first layer.
    Type: Application
    Filed: December 12, 2018
    Publication date: May 9, 2019
    Applicant: NICHIA CORPORATION
    Inventors: Suguru BEPPU, Yoichi BANDO, Hiroto TAMAKI, Takuya NAKABAYASHI
  • Patent number: 7837431
    Abstract: In an impeller 11, an inlet portion and an outlet portion are provided at one end side and the other end side in the axial direction, respectively. An inlet 29 is formed in the lower part of the inlet portion, and an outlet is formed in the side face of the outlet portion. The inlet portion and the outlet portion are partitioned by a flange portion 40. The impeller 11 includes a primary vane 36 and a secondary vane 38. The primary vane 36 defines a spiral primary channel 35 that connects the inlet 29 and the outlet. The secondary vane 38 is formed in a shape that a part of the outer periphery of the outlet portion is gouged inward so as to define a secondary channel 37 connected to the primary channel 35 and extending circumferentially around the outer periphery.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: November 23, 2010
    Assignee: Shinmaywa Industries, Ltd.
    Inventors: Yasuyuki Nishi, Chikara Takebe, Koichi Tamura, Yoichi Tamaki, Akihiro Ando, Arata Funasaka
  • Patent number: 7576406
    Abstract: A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: August 18, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Hideaki Nonami, Masato Hamamoto
  • Patent number: 7238582
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: July 3, 2007
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Patent number: 7089525
    Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: August 8, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
  • Publication number: 20050101097
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Application
    Filed: December 1, 2004
    Publication date: May 12, 2005
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Patent number: 6876067
    Abstract: A semiconductor device improved in reliability is disclosed. The semiconductor device comprises a semiconductor chip, a sealing member which seals the semiconductor chip with resin, a tub having a chip bonding surface for bonding with the chip and a back surface located on the side opposite to the chip bonding surface and exposed to a surface of the sealing member, plural inner leads electrically connected respectively to bonding pads on the semiconductor chip through wires such as gold wires, and plural outer leads integrally connected respectively to the inner leads and projecting to the exterior of the sealing member, wherein surfaces of the tub and the plural inner and outer leads are all coated with palladium plating.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: April 5, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Taiga Arai, Fujiaki Nose, Hiroshi Kikuchi, Yoichi Tamaki
  • Publication number: 20050013688
    Abstract: In an impeller 11, an inlet portion and an outlet portion are provided at one end side and the other end side in the axial direction, respectively. An inlet 29 is formed in the lower part of the inlet portion, and an outlet is formed in the side face of the outlet portion. The inlet portion and the outlet portion are partitioned by a flange portion 40. The impeller 11 includes a primary vane 36 and a secondary vane 38. The primary vane 36 defines a spiral primary channel 35 that connects the inlet 29 and the outlet. The secondary vane 38 is formed in a shape that a part of the outer periphery of the outlet portion is gouged inward so as to define a secondary channel 37 connected to the primary channel 35 and extending circumferentially around the outer periphery.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 20, 2005
    Applicant: ShinMaywa Industries, Ltd.
    Inventors: Yasuyuki Nishi, Chikara Takebe, Koichi Tamura, Yoichi Tamaki, Akihiro Ando, Arata Funasaka
  • Patent number: 6835632
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: December 28, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Publication number: 20040183159
    Abstract: A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.
    Type: Application
    Filed: February 9, 2004
    Publication date: September 23, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Hideaki Nonami, Masato Hamamoto
  • Publication number: 20040079996
    Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.
    Type: Application
    Filed: October 21, 2003
    Publication date: April 29, 2004
    Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
  • Patent number: 6662344
    Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: December 9, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
  • Publication number: 20030222281
    Abstract: A semiconductor device improved in reliability is disclosed. The semiconductor device comprises a semiconductor chip, a sealing member which seals the semiconductor chip with resin, a tub having a chip bonding surface for bonding with the chip and a back surface located on the side opposite to the chip bonding surface and exposed to a surface of the sealing member, plural inner leads electrically connected respectively to bonding pads on the semiconductor chip through wires such as gold wires, and plural outer leads integrally connected respectively to the inner leads and projecting to the exterior of the sealing member, wherein surfaces of the tub and the plural inner and outer leads are all coated with palladium plating.
    Type: Application
    Filed: March 26, 2003
    Publication date: December 4, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Taiga Arai, Fujiaki Nose, Hiroshi Kikuchi, Yoichi Tamaki
  • Publication number: 20030207544
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Application
    Filed: June 13, 2003
    Publication date: November 6, 2003
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Patent number: 6610569
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: August 26, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Patent number: 6573578
    Abstract: A photo semiconductor integrated circuit device has a photodiode portion and amplifier portion, each portion having a buried layer. The impurity concentration and/or depth of the buried layer for the photodiode portion is lower than that of the buried layer for the amplifier portion. As a result, the frequency band width is widened.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: June 3, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Shigeharu Kimura, Kenji Maio, Takeshi Doi, Yoichi Tamaki, Takeshi Shimano
  • Patent number: 6524924
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: February 25, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Publication number: 20020149084
    Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.
    Type: Application
    Filed: March 8, 2002
    Publication date: October 17, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada