Abstract: The semiconductor device includes a first current mirror circuit combining analog power sources and digital power sources to receive small amplitude signals and constant-voltage input signals, a second current mirror circuit for receiving a signal output from the first current mirror circuit and for level-converting the signal from analog power source to digital power source, a first node provided in the first current mirror circuit, a second node provided in the second current mirror circuit, and an inverter circuit for receiving a signal output on the basis of the voltage levels of the first node and the second node and for outputting a CMOS level signal.

Abstract: A clock synchronization circuit includes a first delay circuit for delaying a clock signal and outputting the delayed clock signal, first and second bidirectional delay circuit strings, a first pre-stage delay circuit and a first post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the first bidirectional delay circuit string (BDDA), a second pre-stage delay circuit and a second post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the second bidirectional delay circuit string (BDDB), and a multiplexer, supplied with and multiplexing outputs of the first and second post-stage delay circuits to output the resulting signals. An output signal of the first delay circuit is supplied in common to the first and second pre-stage delay circuits.

Abstract: A clock synchronization circuit includes a first delay circuit for delaying a clock signal and outputting the delayed clock signal, first and second bidirectional delay circuit strings, a first pre-stage delay circuit and a first post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the first bidirectional delay circuit string (BDDA), a second pre-stage delay circuit and a second post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the second bidirectional delay circuit string (BDDB), and a multiplexer, supplied with and multiplexing outputs of the first and second post-stage delay circuits to output the resulting signals. An output signal of the first delay circuit is supplied in common to the first and second pre-stage delay circuits.

Abstract: A 64Mb DRAM includes memory cell array areas 15, sense amplifier areas 16, subword driver areas 17, and cross areas 18. For each horizontal input/output line IOH paraleel to the word line W, throuh holes on the sense amplifiers provide connections between the second metal line hierarchy M2 and the third metal line hierarchy M3. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas 15 in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas 15. In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.

Abstract: The semiconductor device includes a first current mirror circuit combining analog power sources and digital power sources to receive small amplitude signals and constant-voltage input signals, a second current mirror circuit for receiving a signal output from the first current mirror circuit and for level-converting the signal from analog power source to digital power source, a first node provided in the first current mirror circuit, a second node provided in the second current mirror circuit, and an inverter circuit for receiving a signal output on the basis of the voltage levels of the first node and the second node and for outputting a CMOS level signal.

Abstract: A 64 Mb DRAM which comprises memory cell array areas 15, sense amplifier areas 16, subword driver areas 17, and cross areas 18. For each horizontal input/output line IOH parallel to the word line W, through holes on the sense amplifiers provide connections between the second metal line hierarchy M2 and the third metal line hierarchy M3. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas 15 in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas 15. In this input/output line configuration, the greater the number of word lines W selected, the greater the number of bits that can be output.

Abstract: A 64 Mb DRAM includes memory cell array areas 15, sense amplifier areas 16, subword driver areas 17, and cross areas 18. For each horizontal input/output line IOH parallel to the word line W, through holes on the sense amplifiers provide connections between the second metal line hierarchy M2 and the third metal line hierarchy M3. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas 15 in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas 15. In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.

Abstract: A semiconductor integrated circuit device is provided with an internal circuit which receives a source voltage supplied from an external terminal and is activated based on a voltage obtained by reducing the source voltage, and an output circuit which outputs a signal to be outputted produced by the internal circuit, through an external terminal in accordance with a timing signal. In the semiconductor integrated circuit device, a level shift circuit converts the signal produced by the internal circuit to a signal level corresponding to the level of the source voltage supplied from the external terminal. The output circuit outputs the level-shifted signal therefrom using a timing signal of a voltage level corresponding to the source voltage supplied from the external terminal.

Abstract: A semiconductor memory device capable of operating at high speeds, and a sense circuit and a decoder circuit that can be suitably used for the memory device. A latch function is imparted to at least either one of the decoder circuit or the sense circuit in the semiconductor memory device.