Patents by Inventor Yoko Kawano

Yoko Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110010499
    Abstract: A storage system including a storage, has a first power supplier for supplying electronic power, a second power supplier for supplying electronic power when the first power supplier not supplying electronic power to the storage system, a cache memory for storing data sent out from a host, a non-volatile memory for storing data stored in the cache memory, and a controller for writing the data stored in the cache memory into the non-volatile memory when the second supplier supplying electronic power to the storage system, for stopping the writing and for deleting data stored in the non-volatile memory so until a free space volume of the non-volatile memory being not less than a volume of the data stored in the cache memory when the first supplier restoring electronic power to the storage system.
    Type: Application
    Filed: July 7, 2010
    Publication date: January 13, 2011
    Applicant: Fujitsu Limited
    Inventors: Nina Tsukamoto, Yuji Hanaoka, Terumasa Haneda, Atsushi Uchida, Yoko Kawano
  • Publication number: 20100318844
    Abstract: A backup method makes a backup of cache data to a nonvolatile memory by using a controller, the cache data being stored in the volatile memory. The backup method includes writing the cache data stored in the volatility memory in a selected area of the nonvolatile memory, generating party data by operating the parity operations between each of the predetermined parts of the cache data in the volatile memory, verifying whether an error found in the part of the cache data in the nonvolatile memory can be recovered by using the parity data, and rewriting the part of the cache data when the error found in the part of the cache data in the nonvolatile memory cannot be recovered by using the parity data in an area of the nonvolatile memory different from the selected area.
    Type: Application
    Filed: August 3, 2010
    Publication date: December 16, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Shinnosuke MATSUDA, Sadayuki OHYAMA, Kentaro YUASA, Takanori ISHII, Yoko KAWANO, Yuji HANAOKA, Nina TSUKAMOTO, Tomoharu MURO
  • Publication number: 20100306586
    Abstract: A storage apparatus includes a backup processing unit that stores data stored in a first memory into a second memory as backup data upon occurrence of a power failure, a restore processing unit that upon recovery from the power failure restores the backup data backed up in the second memory to the first memory and erases the backup data, and an erasure processing termination unit that terminates the erasure processing upon a power failure occurring during erasure processing for erasing the backup data stored in the second memory, and a re-backup processing unit that re-backs up data in the first memory corresponding to the backup data erased from the second memory before the erasure processing is terminated by the erasure processing termination unit to a location in the second memory subsequent to a last location that contains the backup data which has not been erased.
    Type: Application
    Filed: May 19, 2010
    Publication date: December 2, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Hanaoka, Terumasa Haneda, Atsushi Uchida, Yoko Kawano, Emi Narita
  • Publication number: 20100306570
    Abstract: An asynchronous interface circuit for transferring a data stream between different clock domains, the asynchronous interface circuits includes a data holding circuit for sequentially receiving and transferring data of the data stream in synchronism with a first clock signal, and holding the received data until an input of a next data, an asynchronous memory for sequentially receiving the data held in the data holding circuit in synchronism with the first clock signal and for outputting the data in the order of inputting in synchronism with a second clock signal. The asynchronous interface circuit further includes a monitor for detecting an operating state of the asynchronous memory, and a selector for selecting one of the data output from the asynchronous memory and the data output from the data holding circuit on the basis of a detecting result of the monitor.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 2, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Atsushi UCHIDA, Yuji Hanaoka, Terumasa Haneda, Yoko Kawano, Emi Narita
  • Publication number: 20100299565
    Abstract: A controlling apparatus for controlling a disk array unit includes a cache memory for caching data of the disk array unit; a nonvolatile memory for storing the data in the cache memory; and a control unit for detecting a defective location in the nonvolatile memory where the data is stored defectively and updating information indicating the defection location, for generating an error detection code of the updated information, for writing the generated information and the associated error detection code into an area of the nonvolatile memory different from any area where any information indicating any defective location previously detected and stored into the nonvolatile memory, and for controlling writing the data in the cache memory into a location of the nonvolatile memory designated by any selected one of the information stored in the nonvolatile memory.
    Type: Application
    Filed: August 3, 2010
    Publication date: November 25, 2010
    Applicant: Fujitsu Limited
    Inventors: Tomoharu Muro, Nina Tsukamoto, Yuji Hanaoka, Yoko Kawano
  • Publication number: 20100241806
    Abstract: An information processing apparatus includes, a first storage unit, a second storage unit in which data stored in the first storage unit is backed up, and a memory controller that controls data backup operation. The memory controller divides a transfer source storage area into portions, and provides two transfer destination areas, each of the two transfer destination areas being divided into portions, backs up data in a direction from a beginning address of each divided area of the transfer source storage area to an end address thereof in one of the transfer destination areas provided for each divided area of the transfer source storage area, and backs up data in a direction from the end address of each divided area of the transfer source storage area to the beginning address thereof in the other transfer destination storage area.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 23, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Yoko KAWANO, Yuji HANAOKA, Terumasa HANEDA, Atsushi UCHIDA
  • Publication number: 20100228930
    Abstract: An access control device which writes data to each of predetermined storage block sets in a storage device of which a storage area has been divided into a plurality of storage blocks. The control device includes a management information storage section and an access processing section. The management information storage section stores, for each of said storage blocks, record enable/disable information indicating whether said storage block is a non-defective block in which the data can be recorded or a defective block in which the data cannot be recorded. If the data is written to each of said storage block sets, the access processing section writes the data only to non-defective blocks in said storage block set based on the record enable/disable information stored in said management information storage section.
    Type: Application
    Filed: February 17, 2010
    Publication date: September 9, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Terumasa Haneda, Yoko Kawano