Abstract: An improved sensing device and method for leveling a semiconductor wafer in a chemical mechanical polishing apparatus, which easily detects the change of pressure from a semiconductor wafer contacting with the polishing surface. The present invention includes a polishing platen having a polishing pad on the upper leveled surface thereof, and fixed to a rotatable platen driving shaft. A carrier is rotatably provided on the upper surface of the polishing platen and holding the semiconductor wafer such that the lower surface of the semiconductor wafer is uniformly contacted with the polishing pad. A pressure detecting sensor senses the pressure applied from the semiconductor wafer on the polishing pad and outputs a corresponding signal.

Abstract: The present invention provides an apparatus and a method for classifying and recognizing image patterns using a second-order neural network, thereby achieving high-rate parallel processing while lowering the complexity. The second-order neural network, which is made of adders and multipliers, corrects positional translations generated in a complex-log mapping unit to output the same result for the same object irrespective of the scale and/or rotation of the object. The present invention enables high-rate image pattern classification and recognition based on parallel processing, which is the advantage obtained in neural network models, because consistent neural networks and consistent network structure computation models are applied to all steps from the image input step to the pattern classifying and recognizing step.

Abstract: A wiring structure of a semiconductor device includes a substrate; a first conductive layer formed in the substrate; an insulation film formed on the substrate including the first conductive layer and having a contact hole therein through which the upper surface of the first conductive layer is exposed, wherein the contact hole includes an upper contact hole and a lower contact hole having a shape undercut into the insulation film and thus being wider than the upper contact hole; and a second conductive layer formed on the insulation film so as to thoroughly fill the contact hole and electrically connected to the first conductive layer.

Abstract: A method of forming a metal line structure for use with a semiconductor device includes the steps of: preparing a semiconductor substrate; forming a first line on the semiconductor substrate; forming a plug pattern on the first line; forming at least one insulating layer on an exposed surface of the first line and on the plug pattern; planarizing the insulating layer and, simultaneously, removing the plug pattern to form a contact hole which exposes at least a portion of the first line; and forming a second line in the contact hole such that the second line is configured to couple with the first line.

Abstract: A method of forming an interconnection for a semiconductor device includes the steps of: forming a lower conductive line on a semiconductor substrate and forming a first insulating layer on the semiconductor substrate and the lower conductive line; patterning the first insulating layer to form a first insulating layer pattern which is narrower than the lower conductive line on the lower conductive line; forming a second insulating layer on an overall surface of the substrate and on the first insulating layer pattern, to planarize a surface of the second insulating layer; patterning the second insulating layer to expose a surface of the first insulating layer pattern and to form a first trench wider than the first insulating layer pattern on an upper portion of the first insulating pattern; removing the first insulating layer pattern, to thereby form a second trench at a lower portion of the first trench; and filling the first and second trenches with conductive material, to thereby form an upper conductive li

Abstract: A method for fabricating wiring in a semiconductor device in which a conductor line and a contact hole are formed by self-alignment, includes the steps of: forming an insulating layer on a substrate; forming an etch-step layer on the insulating layer; etching the etch-stop layer of a wiring region connected to a window and the insulating layer to a predetermined thickness; forming a mask layer on the etch-stop layer and the insulating layer; etching the mask layer to remove the mask layer at the central part of the window; and etching the insulating layer of the central part of the window so as to form a contact hole. By applying such a method, a highly improved reliability can be obtained, and a process thereof is simplified by a single photolithography. Also, the contact hole is formed by self-alignment in the lengthwise direction and in the vertical direction of the conductor line.

Abstract: A chemical mechanical polishing apparatus for a semiconductor wafer which is capable of polishing uniformly the surface of the semiconductor wafer and of controlling the polishing amount by providing plurality of rotary drums each wrapped in a polishing cloth on the upper surface of a polishing pad and connecting supporters capable of vertical movement to both ends each rotary drum, and includes a rotatable polishing pad in the planar upper surface of which a plurality of recesses are formed for receiving a semiconductor wafer, a plurality of rotatable polishing units located on the polishing pad for planarizing the surface of the semiconductor wafers, a supporter connected at the endpoints of the rotational polishing units which can make a vertical movement, and a slurry applicator located above the rotational polishing units for putting a slurry thereon.

Abstract: Disclosed is a manufacture and coating method of mechanical products using ferrous alloy in order to improve wear, corrosion, and heat resistances of the mechanical products which are exposed to friction and wear environments with or without lubricating conditions. The mechanical products of the invention include rotation contact parts such as bush and shaft in the inside of caterpillar roller, mechanical seal under high surface pressure, and drawing dice and plug under sliding friction stress. A ferrous alloy composition used for coating in the invention comprises Cr:18.0-42.0 wt %, Mn: 1.0-3.2 wt %, B:3.0-4.5 wt %, Si: 1.0-3.0 wt %, C: less than 0.3 wt %, inevitably incorporated impurities, and Fe for the rest of content. A ferrous alloy composition used for manufacturing bush type product comprises C: less than 4.5%, Si:2.5%, Mn:less than 2%, Cr:0.5-35%, and Fe for the rest of content.