Abstract: An electronic device including: a first pattern part including first mesh lines in which a plurality of first cut line parts are defined; and a second pattern part spaced apart from the first pattern part in a first direction and including a plurality of second cut line parts in which a plurality of second cut line parts are defined. A first reference region is defined in the first pattern part; a second reference region having a same width and area as the first reference region in a second direction crossing the first direction is defined.

Abstract: A double wiping structure of a mascara wand provides an amount of mascara required to be applied to the eyelashes by causing a brush rod provided with a brush to be discharged along a ring member from a container so that mascara adhered to the brush rod is wiped using a first wiper and mascara adhered to the brush is wiped using a second wiper. The double wiping structure prevents mascara adhered to the brush from coming into contact with the inner surface of a wiper body and consequently prevents contamination of the inner surface of the wiper body due to the mascara by causing the ring member to be moved along the inner surface of the wiper body by pressure applied from the brush rod when the brush rod is introduced into and discharged from the container.

Abstract: A file system permission setting method and apparatus, where an access control list (ACL) permission for a parent node is set such that all child nodes of the parent node inherit the ACL permission for the parent node when a semantic type identifier of an access permission for the parent node is a permission root type.

Abstract: A semiconductor device may include a conductive structure on a substrate, a contact plug on the conductive structure, and a magnetic tunnel junction structure on the contact plug. A lower surface of the contact plug may have an area greater than that of an upper surface thereof, and the contact plug may include a capping pattern at least partially covering an upper surface of the conductive structure, a conductive pattern on the capping pattern, and an amorphous metal pattern on the conductive pattern.

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

Abstract: An embodiment relates to a technology for accelerating data communication in a display device and provides a technology for transmitting and receiving at least some information using a communication line for indicating a clock training state.

Abstract: A display apparatus is provided. The display apparatus includes: a display panel, a non-volatile memory, and a controller. The controller is configured to adjust first gain values of the display panel, and obtain two-dimensional color coordinates in a first predetermined color space of the white screen displayed by the display apparatus as white-color coordinates. The controller further adjusts colors displayed by the display apparatus to fit a second predetermined color space, calculates second gain values in the second predetermined color space according to the white-color coordinates, and stores the second gain values in a color-calibration setting in a non-volatile memory of the display apparatus. In response to a selection signal from the display apparatus, the controller reads the color-calibration setting corresponding to the selection signal from the non-volatile memory for execution to perform color calibration on the display apparatus.

Abstract: An extracellular vesicle isolation method using a metal, and a method for isolating extracellular vesicles from various samples using metal affinity are disclosed. An extracellular vesicle isolation method has the advantages of not requiring costly equipment, of being able to be applied without limits on sample quantity, and of being capable of efficiently isolating extracellular vesicles while preserving the shape or properties thereof. Moreover, the method can be combined with existing isolation methods to maximize the efficiency of extracellular vesicle isolation, and can be utilized in disease diagnosis, disease treatment, multi-omics research, and extracellular vesicle property research and the like using the isolated extracellular vesicles.

Abstract: A computer-implemented method is presented for enabling instant and automatic photo sharing between computing devices. The method includes allowing a first user to operate a first computing device to create a plurality of images, the plurality of images including physical characteristics of a second user, transmitting a broadcast message to a plurality of second computing devices, determining whether a match occurs between the first computing device and one or more of the plurality of second computing devices, and establishing a local area network between the first computing device and matched second computing devices. The method further includes automatically and instantly transmitting the plurality of images to the matched second computing devices by priority and sequence determinations, and, upon completion of the transmittal of the plurality of images to the matched second computing devices, terminating the local area network.

Abstract: An apparatus for controlling an inverter to drive a motor includes: a current control processor generating a voltage command for generating d/q axis current detection values, which are obtained by measuring current supplied to the motor, to follow a d/q axis current command for driving the motor, the current control processor converting the voltage command, which is sampled according to a sampling frequency generated based on a voltage vector phase of the voltage command, into a voltage vector corresponding to a point on each vertex and each side of a hexagon in a voltage vector diagram to apply a resulting value to the inverter driving the motor; and a sample frequency computing processor computing the sampling frequency based on the voltage vector phase of the voltage command and a reference number of sampling times during one rotation period of the motor.

Abstract: Provided is a method for cell isolation and morphological analysis. The method includes: providing a substrate with one or more wells; inserting cell isolation devices, each of which has one side patterned with one or more microwells, into the wells; introducing a liquid medium including cells into the wells; allowing the microwells of the cell isolation devices to come into contact with the inner surfaces of the wells such that some of the cells are isolated and trapped at the level of individual cells in the microwells; and observing the morphological changes of the isolated cells.

Abstract: A display device including a substrate including a first display region having a first width, a second display region having a second width smaller than the first width, a peripheral region at a periphery of the first and second display regions, and a dummy region in the peripheral region, a first pixel in the first display region, a second pixel in the second display region, a first control line connected to the first pixel and extending in the first display region, a second control line connected to the second pixel and extending in the second display region, and a dummy line connected to the second control line in the dummy region, wherein the second control line is at a first conductive layer on a first insulating layer, the dummy line is at a second conductive layer on a second insulating layer on the first conductive layer.

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.

Abstract: Embodiments provide a data transmission method and apparatus. The method includes: after obtaining information of a target input port of a data receiving device and information of a target protocol used by a target Internet of Things device connected to the target input port, the data receiving device determines the target input port and the target protocol, and decapsulates, according to the target protocol, a first data packet transmitted by the target Internet of Things device via means of the target input port to obtain data. The data receiving device can adaptively determine a target protocol according to the information of the target protocol used by the target Internet of Things device, without configuring the target protocol for the target Internet of Things device in advance.

Abstract: Provided is a method and apparatus for performing intra-prediction using an adaptive filter. The method for performing intra-prediction includes the steps of: determining whether or not to apply a first filter for a reference pixel value on the basis of information of a neighboring block of a current block; applying the first filter for the reference pixel value when it is determined to apply the first filter; performing intra-prediction on the current block on the basis of the reference pixel value; determining whether or not to apply a second filter for a prediction value according to each prediction mode of the current block, which is predicted by the intra-prediction performance on the basis of the information of the neighboring block; and applying the second filter for the prediction value according to each prediction mode of the current block when it is determined to apply the second filter.

Abstract: The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 ?m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

Abstract: A DNA sequence encoding Der p1 protein having a particular base sequence is codon-optimized for the Pichia pastoris expression system, which is conducive to expressing Der p1 in Pichia pastoris. After gene optimization and adding an activating element to increase the expression of Der p1 in molecular level, it was found that Der p1 is expressed at a higher level as compared with the prior art and has biological activity similar to the natural protein.

Abstract: The present invention provides engineered polypeptides that are useful for the asymmetric synthesis of ?-hydroxy-?-amino acids under industrial-relevant conditions. The present disclosure also provides polynucleotides encoding engineered polypeptides, host cells capable of expressing engineered polypeptides, and methods of producing ?-hydroxy-?-amino acids using engineered polypeptides. Compared to other processes of preparation, the use of the engineered polypeptides of the present invention for the preparation of ?-hydroxy-?-amino acids results in high purity of the desired stereoisomers, mild reaction conditions, low pollution and low energy consumption. So, it has good industrial application prospects.

Abstract: A flocked surface tribo-electric charge generator includes first and second contact surface electrodes; first and second flock fiber support layers a first flock fiber material flocked onto the first flock fiber support layer; a tribo-electrically second different flock fiber material flocked onto the second flock fiber support layer. A tribo-electric charge is generated by intermittent intermeshing/separation of the tribo-electrically diverse flock fiber materials of the first and second flock fiber support layers.

Abstract: A cover for a door frame includes: a sealing member mounted to the door frame; and an inner cover covering at least a portion of the sealing member and at least a portion of the door frame, where a portion of the corner cover is embedded in the sealing member so that the inner cover and the sealing member form a unitary one-piece structure.