Patents by Inventor Yong-Bae Kim

Yong-Bae Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6549413
    Abstract: A package structure includes a heat spreader, a ground plane affixed to the heat spreader, and a flex tape interconnect substrate affixed to the ground plane. An aperture in the ground plane reveals a die attach surface on the heat spreader, and an aperture in the flex tape interconnect structure is aligned with the ground plane aperture such that the aligned apertures together with the revealed ground plane surface define a die cavity. The aperture in the ground plane is formed so as to form aperture walls substantially perpendicular to the ground plane. According to the invention the heat spreader, the ground plane, and the flex tape interconnect substrate have specified characteristics. Particularly, the heat spreader is provided as a metal sheet or strip, usually copper, having a “velvet type” oxide, usually a velvet black copper oxide, on at least the surface of the heat spreader to which the ground plane is to be affixed.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: April 15, 2003
    Assignee: ChipPAC, Inc.
    Inventors: Marcos Karnezos, Yong-Bae Kim
  • Publication number: 20030060057
    Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permitivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used.
    Type: Application
    Filed: October 25, 2002
    Publication date: March 27, 2003
    Inventors: Ivo Raaijmakers, Yong-Bae Kim, Marko Tuominen, Suvi P. Haukka
  • Patent number: 6503840
    Abstract: A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: January 7, 2003
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Hong-Qiang Lu, Yong-Bae Kim, Kiran Kumar, Kai Zhang, Richard Schinella, Philippe Schoenborn
  • Patent number: 6492283
    Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permittivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: December 10, 2002
    Assignee: ASM Microchemistry Oy
    Inventors: Ivo Raaijmakers, Yong-Bae Kim, Marko Tuominen, Suvi P. Haukka
  • Publication number: 20020164877
    Abstract: A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus.
    Type: Application
    Filed: May 2, 2001
    Publication date: November 7, 2002
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Hong-Qiang Lu, Yong-Bae Kim, Kiran Kumar, Kai Zhang, Richard Schinella, Philippe Schoenborn
  • Publication number: 20020127778
    Abstract: A package structure includes a heat spreader, a ground plane affixed to the heat spreader, and a flex tape interconnect substrate affixed to the ground plane. An aperture in the ground plane reveals a die attach surface on the heat spreader, and an aperture in the flex tape interconnect structure is aligned with the ground plane aperture such that the aligned apertures together with the revealed ground plane surface define a die cavity. The aperture in the ground plane is formed so as to form aperture walls substantially perpendicular to the ground plane. According to the invention the heat spreader, the ground plane, and the flex tape interconnect substrate have specified characteristics. Particularly, the heat spreader is provided as a metal sheet or strip, usually copper, having a “velvet type” oxide, usually a velvet black copper oxide, on at least the surface of the heat spreader to which the ground plane is to be affixed.
    Type: Application
    Filed: February 26, 2002
    Publication date: September 12, 2002
    Applicant: ChipPAC, Inc.
    Inventors: Marcos Karenzos, Yong-Bae Kim
  • Publication number: 20010031562
    Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permittivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used.
    Type: Application
    Filed: February 22, 2001
    Publication date: October 18, 2001
    Inventors: Ivo Raaijmakers, Yong-Bae Kim, Marko Tuominen, Suvi P. Haukka