Abstract: A pair of locking arms unitarily extends forwardly from opposite inner edges of the transverse bar in a perpendicular manner and are spaced from two opposite side edges of the shielding plate but abutting against the corresponding side edge of the tongue portion. A front end region of each locking arm further grasps a front edge of the tongue portion and optionally connected to the corresponding grounding terminals. The two opposite ends of the transverse bar are also optimally mechanically and electrically connected to the corresponding grounding terminals. The pair of locking arms may extend from two opposite side edges of the shielding plate or from two opposite end regions of the front edge of the shielding plate alternately.

Abstract: An electronic component includes a first module, a second module and a third module between the first module and the second module. Each of the first module and the second module includes a plurality of conductive pads thereon. A connecting part includes a plate body and a plurality of first tails and a plurality of second tails respectively extending on two opposite sides of the plate body wherein the first tails are soldered upon the first conductive pads and the second tails are soldered upon the second conductive pads, respectively. Each of the first tails and the second tails includes a mounting pad with a through hole therein, and a folded section on the end edge with a solder unit received with a space formed in the folded section and communicatively above the corresponding through hole.

Abstract: A honeycomb rib structure in a rotating gantry of a proton includes a plurality of upper honeycomb ribs and a plurality of lower honeycomb ribs which are mounted in a cylindrical body through a plurality of connecting structures. The plurality of upper honeycomb ribs and the plurality of lower honeycomb ribs are symmetrically arranged, and are spliced by a plurality of basic structures in a regular hexagonal distribution. Connecting nodes between the adjacent basic structures are of a ring structure. Densities of the plurality of upper honeycomb ribs and the plurality of lower honeycomb ribs are adjusted through a density adjustment structure.

Abstract: An electrical connector includes an insulative housing with a plurality of passageways and a plurality of contacts received therein. The housing includes opposite mating surface and mounting surface in the vertical direction. The contact includes an upstanding section retained in the passageway with a spring arm extending from an upper region of the upstanding plate and above the mating surface, and a mounting leg extending from a lower region of the upstanding plate around the mounting surface. The spring arm forms a contacting section around a free end thereof. One additional layer structure extends backwardly from a front end of the spring arm in a compressive folded manner and intimately abuts against the spring arm in the vertical direction.

Abstract: An electrical connector includes an insulative housing with a plurality of passageways and a plurality of contacts received therein. The contact includes an upstanding section retained in the passageway with a spring am extending from an upper region of the upstanding plate and above the mating surface, and a mounting leg extending from a lower region of the upstanding plate around the mounting surface. The spring arm forms a contacting section around a free end thereof. The contact further includes an extension extending from the upstanding section and optimally above the mating surface so as to be located between the spring arm and the mating surface in the vertical direction. The extension and the spring arm are partially overlapped in the vertical direction and results in the capacitance effect therebetween, thus lowering impedance.

Abstract: A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a PN junction with the first-type substrate. The semiconductor device may further include a diode component configured to form a diode with the second-type well. The diode may be connected to the PN junction in a reverse series connection. The second-type may be N-type if the first-type is P-type, and wherein the second-type may be P-type if the first-type is N-type.

Abstract: A panicle separation multi-membrane matrix device and method are provided. The particles isolated may comprise noun-scale particles, such extracellular membrane vesicles, having a size of about 50 to about 150 nm. The vesicles are released by many different cell types, and may be efficiently isolated at high yield and purity according to the present methods from various body fluids (e.g., blood, saliva, breast milk, serum, plasma, ascites fluid, etc.). Such isolated exosome preparations may include biomarkers, such as disease biomarkers (diagnostic markers) for various disease (early stage and late stage cancers, neurological disorders (Parkinson disease, Alzheimer disease), diabetes, pancreatic diseases, renal failure, infectious diseases (HIV, tuberculosis, malaria, hepatitis)). The present methods and devices may be used to detect and monitor animals (human, live-stock, companion animal) for infectious diseases, such as tuberculosis and other diseases.

Abstract: A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

Abstract: A POP structure includes a circuit board, a bottom package structure, a top package structure, and a metal frame structure. The circuit board has a plurality of signal pads and dummy pads. The dummy pads surround the signal pads. The bottom package structure is disposed over the circuit board. The bottom package structure is electrically connected to the signal pads. The top package structure is disposed over the bottom package structure. The top package structure is electrically connected to the bottom package structure. The metal frame structure includes a body and a plurality of terminal pins. The body is located between the top package structure and the bottom package structure. The terminal pins extend outward from an edge of the top package structure to connect the top package structure and the dummy pads of the circuit board.

Abstract: A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

Abstract: A method for performing hulk rerouting in a transport network includes pre-computing routing paths for traffic between multiple source-destination pairs for different time slots and pre-computing an order in which changes of the routing paths are carried out across different time slots, pre-provisioning the routing paths and the order to the respective forwarding network nodes, and generating free network resources according to predefined rides that take into consideration traffic preemption and exploiting the free network resources to bootstrap and/or to facilitate a rerouting sequencing of routing path switching and/or swapping in bulk rerouting across different time slots.

Abstract: A POP structure includes a circuit board, a bottom package structure, a top package structure, and a metal frame structure. The circuit board has a plurality of signal pads and dummy pads. The dummy pads surround the signal pads. The bottom package structure is disposed over the circuit board. The bottom package structure is electrically connected to the signal pads. The top package structure is disposed over the bottom package structure. The top package structure is electrically connected to the bottom package structure. The metal frame structure includes a body and a plurality of terminal pins. The body is located between the top package structure and the bottom package structure. The terminal pins extend outward from an edge of the top package structure to connect the top package structure and the dummy pads of the circuit board.

Abstract: A method for inspecting conductive features of a workpiece includes videographing a part of a workpiece having a plurality of conductive features to capture a workpiece sub-image, in which the workpiece sub-image has one or more feature images respectively corresponding to one or more of the conductive features; finding predetermined feature points corresponding to a part of the feature images among a plurality of predetermined feature points based on the predetermined feature points in a standard workpiece image to locate an area of the standard workpiece image corresponding to the workpiece sub-image; and comparing the corresponding area of the standard workpiece image with the workpiece sub-image, if one or more of the predetermined feature points within the area differ from the one or more first feature images, the workpiece is determined to be a defective workpiece.

Abstract: A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a PN junction with the first-type substrate. The semiconductor device may further include a diode component configured to form a diode with the second-type well. The diode may be connected to the PN junction in a reverse series connection. The second-type may be N-type if the first-type is P-type, and wherein the second-type may be P-type if the first-type is N-type.

Abstract: A LDMOS transistor includes a semiconductor substrate with a first doping type; a plurality of first trenches formed in the semiconductor substrate; a wave-shaped drift region with an increased conductive path and a second doping type formed on the semiconductor substrate between adjacent first trenches and the semiconductor substrate exposed by side and bottom surfaces of the first trenches; a first shallow trench isolation (STI) structure formed in each of the first trenches; a body region with the first doping type formed in semiconductor substrate at one side of the drift region; a gate structure formed over portions of the body region, the drift region and the first STI structure most close to the body region; a source region formed in the body region; and a drain region formed in the drift region at one side of the first STI structure most far away from the body region.

Abstract: Embodiments of the present invention provide a method and a device for detecting SOC of a battery. The method for detecting SOC of a battery includes: determining an initial SOC value of the battery according to a waiting time of the battery; calculating a current SOC value of the battery based on the initial SOC value and a current working current of the battery, denoting as a first SOC value. In embodiments of the present invention, the current of the battery is real-time measured and the SOC value of the battery is calculated by accumulating the current of the battery, in addition, the initial SOC value is calibrated by the waiting time, so that the error of the SOC detection result is reduced, thereby increasing accuracy of the SOC detection result.

Abstract: Disclosed is a BGA package with protective circuitry layouts to prevent cracks of the bottom circuit in the specific area of the substrate leading to package failure and to enhance packaging yield of BGA packages. A chip is disposed on the upper surface of the substrate. A chip projective area is defined inside the bottom surface of the substrate and is established by vertically projecting the edges of the chip on the upper surface to the bottom surface of the substrate. At least an external contact pad vulnerable to thermal stress is located within the chip projective area. A protective area and a wiring area are respectively defined in the chip projective area at two opposing sides of the external contact pad. A plurality of protective mini-pads are arranged in a dotted-line layout and disposed in the projective area to partially surround the external contact pad to avoid thermal stress concentrated on the protective area and to further prevent circuitry cracks in the package structure.

Abstract: A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

Abstract: A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a PN junction with the first-type substrate. The semiconductor device may further include a diode component configured to form a diode with the second-type well. The diode may be connected to the PN junction in a reverse series connection. The second-type may be N-type if the first-type is P-type, and wherein the second-type may be P-type if the first-type is N-type.

Abstract: A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.