Abstract: A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.

Abstract: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.

Abstract: Command decoders are provided. The command decoder includes an input buffer configured for buffering and receiving command address signals having address information and command information at first, second, third, and fourth edges of a clock pulse signal according to a reference voltage, a latch circuit configured for latching the command address signals output from the input buffer at the first and third edges of the clock pulse signal to generate and output latched signals, a first command generator configured for decoding the latched signals output from the latch circuit at the first edge of the clock pulse signal to generate and output a first internal command, and a second command generator configured for decoding the latched signals output from the latch circuit at the third edge of the clock pulse signal to generate and output a second internal command.

Abstract: A semiconductor system includes a first semiconductor chip configured to perform a parallel test according to a first single chip parallel test signal and a multi-chip parallel test signal, and output first data that indicates if the first semiconductor chip passed or failed. A second semiconductor chip is also configured to perform the parallel test according to a second single chip parallel test signal and the multi-chip parallel test signal, and output second data that indicates if the first semiconductor chip passed or failed.

Abstract: A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.

Abstract: A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.

Abstract: An integrated circuit includes: a memory controller configured to determine whether a memory cell included in a semiconductor memory device is defective or not and extract a fail address having positional information of the defective memory cell, in a test mode; and a fail address storage unit configured to store the fail address.

Abstract: A semiconductor memory device includes a first page buffer group including a plurality of page buffers coupled to memory cells of a first memory array through bit lines, a second page buffer group, a coupling circuit configured to couple an output terminal and an inverse output terminal of a selected page buffer of the first page buffer group to a first local I/O line and a first inverse local I/O line, respectively, or an output terminal and an inverse output terminal of a selected page buffer of the second page buffer group to a second local I/O line and a second inverse local I/O line, respectively, in response to a column select signal, and a sense amplifier configured to detect a voltage difference between the first local I/O line and the first inverse local I/O line or between the second local I/O line and the second inverse local I/O line.

Abstract: A nonvolatile memory device includes a number of page buffer groups each comprising a number of normal page buffers, I/O lines corresponding to the respective normal page buffers, and a column decoder generating a column address decoding signal for coupling the normal page buffers of one of the page buffer groups and the respective I/O lines in response to a normal control clock signal.

Abstract: A micro controller includes a first storing circuit configured to store program data for performing a power on operation of a system, and a second storing circuit configured to temporarily store algorithm program data for operation of the system loaded from an external storing means while the system operates in response to control of the first storing circuit.

Abstract: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.

Abstract: A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe signal and output the external data as first internal data in response to an internal clock. The second data input unit is configured to receive the external data at falling edges of the data strobe signal and output the external data as second internal data in response to the internal clock. The clock unit is configured to generate the internal clock using an external clock signal.

Abstract: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.

Abstract: A circuit measures current passing through a memory cell in a NAND flash memory. The circuit includes a decoder and an analog mixer. The decoder is configured to select at least one data line coupled to page buffers and column decoders in accordance with a controlling signal. The analog mixer is configured to output current passing through the selected data line, or to couple all of the data lines to a means for measuring current in accordance with a total current measurement controlling signal.

Abstract: A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe signal and output the external data as first internal data in response to an internal clock. The second data input unit is configured to receive the external data at falling edges of the data strobe signal and output the external data as second internal data in response to the internal clock. The clock unit is configured to generate the internal clock using an external clock signal.

Abstract: It is provided a semiconductor device with the ability to carry out data output operation using a reference clock of which the duty cycle is substantially 50%. The semiconductor device includes a clock buffer for receiving the external clock to generate an internal clock; a delay locked loop circuit for receiving the internal clock to generate a delay locked clock, a controlling unit for generating a control signal, a data output unit for output of data synchronized with a reference clock, and a clock transfer circuit for receiving the delay locked clock to output the reference clock in response to the control signal wherein the clock transfer circuit corrects the duty cycle of the delay locked clock based on a duty cycle information of the reference clock.

Abstract: A circuit for removing noise from an input signal includes a falling edge signal delaying circuit configured to output a first delay output signal generated by delaying a falling edge of a first output signal for a preset time; a falling edge sensing circuit configured to sense the falling edge of the first output signal, and generate a pulse signal in accordance with the sense; a flip-flop configured to output the first delay output signal in accordance with an input clock signal; and a first logic operation circuit configured to perform a logic operation on an output signal of the flip-flop and the first output signal delayed for the preset time, thereby generating a second output signal.

Abstract: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.

Abstract: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.

Abstract: A circuit for removing noise from an input signal includes a falling edge signal delaying circuit configured to output a first delay output signal generated by delaying a falling edge of a first output signal for a preset time; a falling edge sensing circuit configured to sense the falling edge of the first output signal, and generate a pulse signal in accordance with the sense; a flip-flop configured to output the first delay output signal in accordance with an input clock signal; and a first logic operation circuit configured to perform a logic operation on an output signal of the flip-flop and the first output signal delayed for the preset time, thereby generating a second output signal.