Abstract: A micro controller includes a first storing circuit configured to store program data for performing a power on operation of a system, and a second storing circuit configured to temporarily store algorithm program data for operation of the system loaded from an external storing means while the system operates in response to control of the first storing circuit.

Abstract: A circuit measures current passing through a memory cell in a NAND flash memory. The circuit includes a decoder and an analog mixer. The decoder is configured to select at least one data line coupled to page buffers and column decoders in accordance with a controlling signal. The analog mixer is configured to output current passing through the selected data line, or to couple all of the data lines to a means for measuring current in accordance with a total current measurement controlling signal.

Abstract: It is provided a semiconductor device with the ability to carry out data output operation using a reference clock of which the duty cycle is substantially 50%. The semiconductor device includes a clock buffer for receiving the external clock to generate an internal clock; a delay locked loop circuit for receiving the internal clock to generate a delay locked clock, a controlling unit for generating a control signal, a data output unit for output of data synchronized with a reference clock, and a clock transfer circuit for receiving the delay locked clock to output the reference clock in response to the control signal wherein the clock transfer circuit corrects the duty cycle of the delay locked clock based on a duty cycle information of the reference clock.

Abstract: The I/O compression test circuit performs test on global I/O lines divided into groups after failure occurs, thereby improving repair efficiency. The configuration of the test circuit is simplified by using a reset circuit, reducing the delay time, and thereby decreasing test time. Additionally, two strobe signals enable the I/O compression test circuit to perform a stable operation.

Abstract: Disclosed are a main amplifier and a semiconductor device employing the main amplifier. The main amplifier is arranged between a plurality of pairs of local input/output lines and a global input/output line. The main amplifier comprises a main amplifier pre-charge unit for pre-charging the main amplifier in response to inputted pre-charge control signals; an input/output sense amplifier enabled by enable signals for sensing a first data signal transmitted from the plurality of pairs of input/output lines of a plurality of memory banks, amplifying the sensed first data signal, and outputting the amplified first data signal as a second data signal of a first potential level; and an input/output driver for pull-down or pull-up driving the global input/output line in response to the second data signal from the input/output sense amplifier. The main amplifier is connected in common to the plurality of pairs of local input/output lines for taking charge of the plurality of memory banks.

Abstract: A clock synchronization device is disclosed which optimizes clock skew without increasing the number of unit delay cells by using an auxiliary delay circuit when a clock signal of ultra low frequency is inputted and improves operation frequency by using different programmable dividers to operate at different division rates when clock signals of high frequency and low frequency are inputted. Additionally, the optimum clock synchronization device may be embodied by using a replica delay unit corresponding with the package type.

Abstract: Provided is a write circuit of a DDR SDRAM, in which a clock domain crossing is generated from a writing driver during a data write operation and a proper data is always transferred to a gio bus line by using the delay of an internal data strobe signal's falling for a certain amount of time as an input data strobe bar signal. Moreover, by using a skew detection circuit, it is possible to detect a skew tDQSS between a clock and a data strobe, and the skew tDQSS is automatically compensated by the skew compensation circuit. From the perspective of a timing error between the clock and the data strobe, therefore, the write operation of the DDR SDRAM has twice the timing margin (0.5tCK) compared to that of the related art. This means that a stable, high-speed write operation of the DDR SDRAM can be made possible.

Abstract: A delay-locked loop circuit may include a frequency doubler for increasing a frequency of a clock signal and a frequency divider for decreasing the frequency of the clock signal. The delay-locked loop circuit can be selectively operated in a low frequency and a high frequency by the frequency doubler and the frequency divider.

Abstract: A wafer burn-in test mode circuit includes a command decoder, an address latch circuit configured to latch an address signals, a register configured to store a wafer burn-in address signal from the address latch, a wafer burn-in test mode entry circuit configured to generate a wafer burn-in test mode entry signal according to the wafer burn-in address signal and a command signal from the command decoder, a shift registers configured to shift the wafer burn-in address signal according to the wafer burn-in test mode entry signal and a wafer burn-in clock signal, a wafer burn-in test priority decision circuit configured to output test priority signals according to output signals of the shift registers, and a decoder configured to decode the output signals of the shift registers according to the priority signals and configured to output wafer burn-in test signals corresponding to a wafer burn-in test item.

Abstract: A voltage supply circuit is capable of improving an operating speed of the circuit while lowering power consumption. An internal power supply voltage that is dropped and an internal ground voltage that is raised, from an external power supply, are generated and then supplied to an internal circuit. Therefore, when the circuit is driven, a swing width of a signal is reduced to reduce a dynamic power. When the internal circuit is driven at a low voltage, the back bias of a transistor is varied to lower the threshold voltage. Thus, the operating speed can be improved. Also, in a standby mode, the threshold voltage is increased to minimize the amount of current flowing at a sub-threshold voltage below the threshold voltage, thus reducing a static power.

Abstract: A new Delay Locked Loop (DLL) circuit is interoperable with products having different applications by controlling the count of a DLL circuit according to the operating clock frequency. Therefore, the products having different applications can be manufactured in the same manufacturing processes and test processes. The DLL circuit includes: a clock buffer for receiving an external clock signal; a first frequency divider for dividing the buffered clock signal; a phase detector for detecting phase error; a DLL controller for generating shift-control signals; a delay line for locking between an internal clock signal and an external clock signal; a second frequency divider for dividing the internal clock signal; and a replica unit for modeling tAC path.

Abstract: The I/O compression test circuit performs the test on the global I/O lines divided into groups when failure occurs, thereby improving the repair efficiency. Also, since the configuration of the test circuit is simplified by using a reset circuit, the delay time generated by a logic circuit device is reduced, thereby decreasing test time. Additionally, two sampling clock signals enable memory cells to perform a stable operation on skew between global I/O lines or glitch generated in internal circuits.

Abstract: A new Delay Locked Loop (DLL) circuit is interoperable with products having different applications by controlling the count of a DLL circuit according to the operating clock frequency. Therefore, the products having different applications can be manufactured in the same manufacturing processes and test processes. The DLL circuit includes: a clock buffer for receiving an external clock signal; a first frequency divider for dividing the buffered clock signal; a phase detector for detecting phase error; a DLL controller for generating shift-control signals; a delay line for locking between an internal clock signal and an external clock signal; a second frequency divider for dividing the internal clock signal; and a replica unit for modeling tAC path.

Abstract: A wafer burn-in test mode circuit is described. In a wafer burn-in test mode, an output at respective stages may be decoded using a single address signal in a shift register to minimize the number of an address necessary to decode a test item. Therefore, the limit of a burn-in apparatus having a small number of a channel may be overcome. Various test items may be supported with only a single address signal.

Abstract: A clock synchronization device is disclosed which optimizes clock skew without increasing the number of unit delay cells by using an auxiliary delay circuit when a clock signal of ultra low frequency is inputted and improves operation frequency by using different programmable dividers to operate at different division rates when clock signals of high frequency and low frequency are inputted. Additionally, the optimum clock synchronization device may be embodied by using a replica delay unit corresponding with the package type.

Abstract: The present invention relates to a voltage supply circuit capable of improving an operating speed of the circuit while lowering power consumption. An internal power supply voltage that is dropped and an internal ground voltage that is raised, from an external power supply, are generated and then supplied to an internal circuit. Therefore, when the circuit is driven, a swing width of a signal is reduced to reduce a dynamic power. When the internal circuit is driven at a low voltage, the back bias of a transistor is varied to lower the threshold voltage. Thus, the operating speed can be improved. Also, in a standby mode, the threshold voltage is increased to minimize the amount of current flowing at a sub-threshold voltage blow the threshold voltage, thus reducing a static power.

Abstract: A synchronous semiconductor device which can distribute a clock signal inputted through an input pad from a top portion, not from a center portion, to bottom, left, and right portions of a chip. The synchronous semiconductor device comprises a frequency dividing section for dividing of an input clock signal, buffer section for distributing a divided clock signal outputted from the frequency dividing section to necessary parts of a chip, and frequency multiplying section, receiving the divided clock signal outputted from the frequency dividing section and the buffer section, for adjusting a pulse width thereof with a frequency identical to that of the input clock signal. The frequency of the clock signal is divided by the frequency dividing section, and the divided clock signal is distributed from a top portion of the chip to left, right, and bottom portions of the chip.