Abstract: A Schmitt trigger circuit having an input coupled to a current summing junction. A trickle current source generates a trickle current applied to the current summing junction. A bandgap current source generates a bandgap current applied to the current summing junction (wherein the bandgap current is fixed when a supply voltage exceeds a threshold). A variable current source generates a variable current applied to the current summing junction (wherein the variable current varies dependent on the supply voltage). At the current summing junction, the variable current is offset against the trickle and bandgap currents with respect to generating a voltage that is sensed at the Schmitt trigger circuit input.

Abstract: A probe insertion auxiliary and a method of probe insertion are provided. A light source illuminates holes on a lower die to make the position of the holes clear for an operator. The probe insertion auxiliary includes a bottom and a clamp pair disposed on the bottom. The clamp pair has two clamp parts. The two clamp parts define a slit for disposing a probe chassis. Furthermore, the two clamp parts and the bottom form a space. A light source is disposed inside the space for illuminating the holes.

Abstract: Embodiments include a method for adjusting layout size of a hyperlink. The method comprises: displaying at least one hyperlink in a user interface; detecting a touch operation for the at least one hyperlink, and extracting position coordinates of a touch point formed by the touch operation on the user interface; determining a target hyperlink from the at least one hyperlink, and determining the precision of the touch operation with respect to the target hyperlink based on the position coordinates of the touch point; and adjusting layout size of the target hyperlink based on the determined precision. A hyperlink layout in a web page can be adapted to the touch precision of user's finger automatically, which facilitates the recognition of hyperlinks by the user's finger.

Abstract: An electronic circuit can be coupled to an energy harvesting device. The output of the energy harvesting device can provide a damped oscillating waveform elicited from a transient stimulus applied to the energy harvesting device, such as in response to mechanical shock or mechanical impact excitation. A first switch can be coupled between the energy harvesting device and an inductor and configured to selectively connect the input node to the inductor. A second switch can be coupled between the inductor and an energy storage device, the second switch configured to selectively couple the inductor to the energy storage device. A control circuit can be coupled to the first and second switches, such as configured to operate the first and second switches according to one or more of an over bias flip technique, a half bias flip technique, or a bias flip technique.

Abstract: Embodiments of the present invention provide a method, computer program product, and computer system for reclaiming resources during virtual machine decommission. The method includes determining a virtual machine (VM) resource utilization and a cluster utilization. If the VM resource utilization is less than a first predetermined threshold and the cluster utilization is greater than a second predetermined threshold, the method then determines whether an active timer exists. If the active timer exists and has expired, then dynamic decommission of the VM is triggered.

Abstract: A probe insertion auxiliary and a method of probe insertion are provided. A light source illuminates holes on a lower die to make the position of the holes clear for an operator. The probe insertion auxiliary includes a bottom and a clamp pair disposed on the bottom. The clamp pair has two clamp parts. The two clamp parts define a slit for disposing a probe chassis. Furthermore, the two clamp parts and the bottom form a space. A light source is disposed inside the space for illuminating the holes.

Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer overlying the base dielectric layer, and a second dielectric layer overlying the first dielectric layer. A first overlay mark is positioned within the first dielectric layer, and a second overlay mark is positioned within the second dielectric layer, where the second overlay mark is offset from the first overlay mark. First and second blocks are positioned within the base dielectric layer, where the first overlay mark directly overlays the first block and the second overlay mark directly overlays the second block.

Abstract: Embodiments of the present invention provide a method, computer program product, and computer system for reclaiming resources during virtual machine decommission. The method includes determining a virtual machine (VM) resource utilization and a cluster utilization. If the VM resource utilization is less than a first predetermined threshold and the cluster utilization is greater than a second predetermined threshold, the method then determines whether an active timer exists. If the active timer exists and has expired, then dynamic decommission of the VM is triggered.

Abstract: A Schmitt trigger circuit having an input coupled to a current summing junction. A trickle current source generates a trickle current applied to the current summing junction. A bandgap current source generates a bandgap current applied to the current summing junction (wherein the bandgap current is fixed when a supply voltage exceeds a threshold). A variable current source generates a variable current applied to the current summing junction (wherein the variable current varies dependent on the supply voltage). At the current summing junction, the variable current is offset against the trickle and bandgap currents with respect to generating a voltage that is sensed at the Schmitt trigger circuit input.

Abstract: An electronic device includes a first circuit to generate an output control signal when a first voltage across a first capacitor receiving an input current exceeds a threshold voltage, in response to an input signal having a first logic level. The input current is proportional to a frequency of the input signal. A second circuit is to generate an output reset signal when a second voltage across a second capacitor receiving the input current exceeds the threshold voltage, in response to the input signal having a second logic level. A flip flop is to generate a signal output as having the first logic level in response to the output control signal, and to reset and generate the signal output as having the second logic level in response to the output reset signal.

Abstract: An electronic device includes a first circuit to generate an output control signal when a first voltage across a first capacitor receiving an input current exceeds a threshold voltage, in response to an input signal having a first logic level. The input current is proportional to a frequency of the input signal. A second circuit is to generate an output reset signal when a second voltage across a second capacitor receiving the input current exceeds the threshold voltage, in response to the input signal having a second logic level. A flip flop is to generate a signal output as having the first logic level in response to the output control signal, and to reset and generate the signal output as having the second logic level in response to the output reset signal.

Abstract: A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.

Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer overlying the base dielectric layer, and a second dielectric layer overlying the first dielectric layer. A first overlay mark is positioned within the first dielectric layer, and a second overlay mark is positioned within the second dielectric layer, where the second overlay mark is offset from the first overlay mark. First and second blocks are positioned within the base dielectric layer, where the first overlay mark directly overlays the first block and the second overlay mark directly overlays the second block.

Abstract: Placement of virtual machines on physical hosts are based on differing initial policies and optimization policies set by a system administrator to more efficiently utilize system resources and serve the needs of different workloads. A scheduler mechanism allows a system administrator to select different initial placement policies for one or more host groups of physical hosts. The scheduler mechanism utilizes an optimizer that monitors host performance and adjusts the placement of virtual machines according to another set of optimization policies similarly selected by the system administrator for each of the host groups.

Abstract: Placement of virtual machines on physical hosts are based on differing initial policies and optimization policies set by a system administrator to more efficiently utilize system resources and serve the needs of different workloads. A scheduler mechanism allows a system administrator to select different initial placement policies for one or more host groups of physical hosts. The scheduler mechanism utilizes an optimizer that monitors host performance and adjusts the placement of virtual machines according to another set of optimization policies similarly selected by the system administrator for each of the host groups.

Abstract: A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.

Abstract: Methods for performing geodesic edits and corresponding systems and computer-readable mediums. A method includes receiving a CAD model including at least a three-dimensional (3D) surface. The method includes receiving an edit of a first geodesic feature from a user and in response to the edit, performing a hierarchy-based update to the CAD model, including performing a corresponding edit to at least one other feature of the CAD model based on the edit to the first geodesic feature to produce an updated CAD model. The method includes storing the updated CAD model.

Abstract: Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list of hardware design outputs. Furthermore, a modified netlist involving logical paths is generated by determining whether a gate is selected as an insertion point, and selecting a fault type, which is part of the efficiency vector for the selected gate in the netlist and inserting a mutant. Additionally, a fault simulation is performed and the quality parameter for the verification environment is determined from the fault simulation and the simulation result data.

Abstract: A reference current path carries a reference current. A first transistor is coupled to the reference current path. A second transistor is also coupled to the reference current path. The first and second transistors are connected in parallel to carry the reference current. The first transistor is biased by a first voltage (which is a bandgap voltage plus a threshold voltage). The second transistor is biased by a second voltage (which is a PTAT voltage plus a threshold voltage). The first and second transistors are thus biased by voltages having different and opposite temperature coefficients with a result that the temperature coefficients of the currents flowing in the first and second transistors are opposite and the reference current accordingly has a low temperature coefficient.

Abstract: The invention relates to a method for refining a feed oil having contaminants therein. In the method, the feed oil is exposed to reducing conditions at elevated temperature and pressure so as to reduce at least some of said contaminants. The resulting oil is then degassed under reduced pressure under non-oxidising conditions and the resulting oil extracted with water so as to produce a refined oil.