Abstract: Disclosed is a method for manufacturing a back side illumination image sensor. The method includes defining a pixel area by forming a first isolation area in a first substrate; forming a photo detecting unit buried in the pixel area; forming an ion implantation layer on the photo detecting unit; growing a second substrate on the first substrate having the ion implantation layer; forming a logic unit electrically connected to the first substrate on the second substrate; forming an insulting layer and an interconnection on the second substrate; and exposing the photo detecting unit by grinding a backside of the first substrate.

Abstract: Disclosed are a non-volatile semiconductor memory device capable of simplifying the complicated structure of a transistor, and a fabrication method for the same.

Abstract: A method for fabricating a MOS transistor is suitable for modifying the configuration of a gate electrode. The method includes coating a first oxide layer on a semiconductor substrate and removing a predetermined width of the first oxide layer; forming an LDD region in the substrate; forming a gate spacer on the substrate; forming a channel in the LDD region, forming a gate oxide layer; forming a polysilicon gate electrode; and forming source/drain diffusion regions. Accordingly, a line width of the gate electrode can be reduced without employing lithography of high precision, and an area reserved for salicide can be maximally secured on the gate and source/drain regions.

Abstract: A Cu line in a semiconductor device and method of forming same are disclosed. The method may include forming an insulating interlayer on a semiconductor substrate, forming a contact hole and a trench in the insulating interlayer in sequence, forming a short-circuit preventing layer on the insulating interlayer including the contact hole and the trench, forming a spacer on a sidewall of the trench by etching the short-circuit preventing layer, forming a Cu line layer over the semiconductor substrate including the contact hole and the trench, planarizing the Cu line layer by CMP, and forming a Cu-diffusion preventing capping layer over the semiconductor substrate including the Cu line layer.

Abstract: Disclosed is a method for placing dummy patterns in a semiconductor device layout. More specifically, the method places the dummy patterns densely between main patterns in accordance with a sequence and configuration. The method includes placing vertical dummies having a greater length than width in a region other than main patterns to form a first layout, removing the vertical dummies within a first distance from the main patterns to form a second layout, placing horizontal dummies having a greater length than width in a vacant space of the second layout to form a third layout, and removing the horizontal dummies within a second distance from the main patterns in the third layout. The method prevents and/or inhibits pattern deformation.

Abstract: A method for manufacturing a metal line of a semiconductor device includes forming an interlayer dielectric layer over the whole surface of a semiconductor substrate including a first metal line. A plurality of trenches are formed in trench areas each having a predetermined depth from a surface thereof by selectively removing portions of the interlayer dielectric layer. A first metal film is formed in the plurality of trenches. A first photoresist pattern is formed over the interlayer dielectric layer exposing contact areas and the first metal line. Via holes are formed in the contact areas by etching the interlayer dielectric layer using the first photoresist pattern and the first metal film as masks. A second metal film is formed in the via holes. Accordingly, misalignment of masks caused during formation of the metal line can be restrained, thereby minimizing the defect rate and improving yield.

Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a gate pattern formed on a semiconductor substrate, a first impurity-doped region formed in the substrate on one side of the gate pattern and a second impurity-doped region formed in the substrate on the other side of the gate pattern, a salicide shielding film pattern partially covering either the first impurity-doped region or the second impurity-doped region, an insulating film formed on the semiconductor substrate, the insulating film including a first hole which exposes the salicide shielding film pattern, and a second hole which partially exposes the first impurity-doped region or the second impurity-doped region that is not covered by the salicide shielding film pattern, and a first line coming in contact with the salicide shielding film pattern through the first hole.

Abstract: A method of manufacturing a semiconductor device for decreasing a chip area by changing a connecting structure of pull up transistors and pull down transistors are disclosed. The semiconductor device can include pull up and pull down transistors including a first pull down transistor, a first pull up transistor, a second pull up transistor and a second pull down transistor, the first pull down transistor, the first pull up transistor, the second pull up transistor and the second pull down transistor being sequentially arranged in a series form on a SRAM, and line type contacts and metal lines formed on the respective pull up and pull down transistors.

Abstract: Inductors in semiconductor devices and methods of manufacturing the same are disclosed. A disclosed inductor includes: a semiconductor substrate; a first dielectric layer on the substrate; a first spiral shaped, metal wire on the first dielectric layer; and a second dielectric layer on the first metal wire and the first dielectric layer. The second dielectric layer has a spiral shaped contact hole exposing the first metal wire. The inductor also includes a second metal wire on the second dielectric layer and electrically connected to the first metal wire through the contact hole. A boundary line of the second metal wire is substantially aligned with a boundary line of the first metal wire.