Patents by Inventor YongGil Lee

YongGil Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12254330
    Abstract: An electronic device displays a first screen is provided. The electronic device includes a list of one or more second applications in a display based on a first application, the second applications being different from the first application. The electronic device displays, in response to a first input of selecting one application of the one or more second applications based on the list, a second screen based on execution of the selected application in the display. The electronic device identifies information indicating at least one application switchable from the second screen within the first application, in response to a second input executing a third application based on the second screen. The electronic device identifies whether to switch from the second screen to a third screen based on execution of the third application to initiate the execution of the third application.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: March 18, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Younggyun Lee, Wontaek Kim, Changmin Choi, Yonggil Han
  • Publication number: 20250081422
    Abstract: An electronic device may include: a printed circuit board; an electronic component disposed on one surface of the printed circuit board; a shield frame disposed on the one surface of the printed circuit board while surrounding the electronic component, the shield frame including a frame opening; a shielding sheet disposed on, directly or indirectly, one surface of the shield frame, and having at least a portion which is disposed in one direction of the frame opening of the shield frame to cover the frame opening; and a heat transfer material disposed between at least the electronic component and the shielding sheet. The shield frame may include an opening side area which may include: a first surface in which the shielding sheet is disposed; and a second surface opposite the first surface.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Inventors: Muyeol LEE, Eunsoo PARK, Byungwoo LEE, Jinwan AN, Jiwoo LEE, Yonggil HAN
  • Patent number: 7169651
    Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: January 30, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: HyungJun Park, HyeongNo Kim, SangBae Park, YongGil Lee, KyungSoo Rho, JunYoung Yang, JinHee Won
  • Patent number: 7087461
    Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. Each lead of the lead frame has a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion. After a wire bonding step and an encapsulating step are conducted, a second metal layer is selectively plated on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product. Then, the third portion of each lead is selectively etched away such that the first portion and the second portion are electrically isolated from each other. Finally, a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: August 8, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: HyungJun Park, HyeongNo Kim, SangBae Park, YongGil Lee, KyungSoo Rho, JunYoung Yang, JinHee Won
  • Publication number: 20060035414
    Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
    Type: Application
    Filed: August 11, 2004
    Publication date: February 16, 2006
    Inventors: HyungJun Park, HyeongNo Kim, SangBae Park, YongGil Lee, KyungSoo Rho, JunYoung Yang, JinHee Won