Method for manufacturing stacked package structure
A method for manufacturing a stacked package structure is disclosed, comprising: forming a first chip package structure, comprising: providing a chip carrier having a first and a second surface in opposition to each other; forming bonding wires on the first surface; providing at least one chip on and electrically connected to the first surface; and forming an encapsulant covering the first surface, the chip and the bonding wires, wherein a top end of each bonding wire is exposed at a surface of the encapsulant; forming a plurality of electrical connections respectively deposed on the top end of each bonding wire; and providing a second chip structure electrically jointed with the electrical connections and stacked on the first chip package structure.
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This application is a continuation-in-part of U.S. application Ser. No. 11/409,933, filed on Apr. 24, 2006, hereby incorporated by reference as it fully set forth herein.
FIELD OF THE INVENTIONThe present invention relates to a system-in-package (SiP) structure and a method for manufacturing the same, and more particularly, to a stacked package structure and a method for manufacturing the same.
BACKGROUND OF THE INVENTIONThe demand for low cost, small size, and more functionality has become the main driving force in the electronic industry. To achieve such goals, advanced packaging techniques like flip chip, chip scale package, wafer level packaging, and 3D packages have been developed. The 3D packaging technique is developed to integrate dies, packages and passive components into one package, in other words, to achieve system in a package solution. The integration can be made in side-by-side, stacked, or both manners. The outstanding advantages of 3D package are small footprint, high performance and low cost.
FIGS. 1 to 3 are schematic flow diagrams showing the process for manufacturing a conventional stacked package structure. In the fabrication of a conventional stacked package structure 250, a chip package structure 100 is firstly provided typically, in which the chip package structure 100 is generally a chip scale package (CSP). The chip package structure 100 mainly includes a substrate 102, a chip 104, an encapsulant 108 and solder balls 110, such as shown in
Next, another chip package structure 200 is provided, in which the chip package structure 200 is mainly composed of a substrate 202, a chip 204, an encapsulant 208 and solder balls 210, such as shown in
Then, the chip package structure 100 is stacked on the chip package structure 200, and the solder balls 110 of the chip package structure 100 are respectively connected to the corresponding connection pads 216. Subsequently, a reflow step is performed, so as to connect the solder balls 110 of the chip package structure 100 to the connection pads 216 of the chip package structure 200 to complete the stacked package structure 250.
However, in the connection treatment of the chip package structure 100 and the chip package structure 200, warpage will occur in the chip package structure 100 and the chip package structure 200, especially the chip package structure 100. Furthermore, the room between the substrate 102 of the chip package structure 100 and the substrate 202 of the chip package structure 200 is still large, and the connection locations between the chip package structure 100 and the chip package structure 200 are at the outer region, so that a cold joint occurs between the chip package structure 100 and the chip package structure 200. As a result, the reliability of the stacked package structure is seriously deteriorated, the yield of the package process is greatly reduced, and the cost is substantially increased.
SUMMARY OF THE INVENTIONTherefore, one objective of the present invention is to provide a method for manufacturing a stacked package structure, which can reduce the area occupied by the package structure to greatly decrease the area of a printed circuit board.
Another objective of the present invention is to provide a method for manufacturing a stacked package structure, which can integrate the connection between an upper chip package structure and a bottom chip package structure.
Still another objective of the present invention is to provide a method for manufacturing a stacked package structure, which can effectively avoid warpage from occurring in the connection of chip package structures, and prevent a cold joint condition from occurring between the chip package structures, so as to greatly enhance the yield of the stacked package structure.
According to the aforementioned objectives, the present invention provides a method for manufacturing a stacked package structure, comprising: forming a first chip package structure, comprising: providing a first chip carrier having a first surface and a second surface in opposition to each other; forming a plurality of bonding wires on the first surface of the first chip carrier; providing at least one first chip on and electrically connected to the first surface of the first chip carrier, wherein each bonding wire is higher than the at least one first chip in altitude; and forming an encapsulant covering the first surface of the first chip carrier, the at least one first chip and the bonding wires, wherein at least one top end of each bonding wire is exposed at a surface of the encapsulant; and providing a second chip package structure electrically connected to and stacked on the first chip package structure.
According to a preferred embodiment of the present invention, the step of providing the second chip structure comprises: providing a second substrate having a first surface and a second surface in opposition to each other; forming a plurality of electrical connection devices on the first surface of the second substrate; providing at least one second chip on and electrically connected to the first surface of the second substrate, wherein each electrical connection device is higher than the at least one second chip in altitude; and forming another encapsulant covering the first surface of the second substrate, the at least one second chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the another encapsulant.
BRIEF DESCRIPTION OF THE DRAWINGSThe foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIGS. 1 to 3 are schematic flow diagrams showing the process for manufacturing a conventional stacked package structure.
FIGS. 4 to 9b are schematic flow diagrams showing the process for manufacturing a stacked package structure in accordance with a first preferred embodiment of the present invention, wherein
The present invention discloses a stacked package structure and a method for manufacturing the same. In order to make the illustration of the present invention more explicit and complete, the following description is stated with reference to FIGS. 4 to 12c.
Referring to FIGS. 4 to 9b and
Next, a chip structure 308 is attached to a central region of the surface 326a of the substrate 300a, and several wires 316 are formed to connect the chip structure 308 and pads (not shown) at the surface 326a of the substrate 300a by, for example, a wire bonding method, so as to electrically connect the chip structure 308 and the substrate 300a. Alternatively, the wires 316 also can be replaced by bumps (not shown), and the chip structure 308 can be electrically connected to the substrate 300a by a flip-chip method. The passive devices 310 according to the requirements are provided and attached to the surface 326a of the substrate 300a at the periphery of the chip structure 308, in which the passive devices 310 may be resistors, inductors or capacitors, for example. In the present embodiment, the chip structure 308 is a multi-chip structure including a chip 302 and a chip 306, in which the chip 302 and the chip 306 can be jointed by an adhesion layer 304, and a material of the adhesion layer 304 can be, for example, epoxy. However, it is worthy of note that the chip structure of the present invention may be composed of a single chip. A plurality of electrical connection devices 312a are formed in the outer region of the surface 326a of the substrate 300a, in which the electrical connection devices 312a are preferably located at the periphery of the chip structure 308 and the passive devices 310, such as shown in
However, in the other embodiments of the present invention, various types of electrical connection devices, such as electrical connection devices 312b shown in
Next, such as shown in
In the exemplary embodiment, after the encapsulant 318 is formed, several connection bumps 322a or solder balls are formed and respectively attached on the top end 314a of each electrical connection device 312a, so as to complete the chip package structure 324a, such as shown in
A chip package structure 420a is formed by a method similar to the method for manufacturing the chip package structure 324a. The chip package structure 420a is mainly composed of a substrate 400, a chip structure 408 and electrical connection devices 412a. The substrate 400 has a surface 422 and a surface 424 in opposition to each other. A chip structure 408 is attached to a central region of the surface 422 of the substrate 400, and several wires 416 are formed to connect the chip structure 408 and pads (not shown) at the surface 422 of the substrate 400 by, for example, a wire bonding method, so as to electrically connect the chip structure 408 and the substrate 400. In the present embodiment, the chip structure 408 is a multi-chip structure including a chip 402 and a chip 406, in which the chip 402 and the chip 408 can be jointed by an adhesion layer 404, and a material of the adhesion layer 404 can be, for example, epoxy. It is worthy of note that the chip structure of the present invention may be composed of a single chip. A plurality of electrical connection devices 412a are formed in the outer region of the surface 422 of the substrate 400. In a preferred embodiment of the present invention, the passive devices 410 according to the requirements are provided and attached to the surface 422 of the substrate 400 at the periphery of the chip structure 408, in which the passive devices 410 may be resistors, inductors or capacitors, for example. The electrical connection devices 412a are preferably located at the periphery of the chip structure 408 and the passive devices 410, and the electrical connection devices 412a must be higher than the chip structure 408 in altitude, such as shown in
In the other embodiments, such as shown in
In the other embodiments of the present invention, various types of electrical connection devices or any combination of these electrical connection devices, such as electrical connection devices 412b of the chip package structure 420b (such as shown in
In the stacked package structure of the present invention, a chip 426 and passive devices 428 can be further set on the surface 424 of the substrate 400, and connection bumps 322b larger than the connection bumps 322a are used and the height of the connection bumps 322b is larger than that of the chip 426, so as to prevent the chip 426 and the passive devices 428 from contacting the underlying chip package structure. In the embodiments, a chip package structure 421a such as shown in
In some embodiment of the present invention, the encapsulant 318 may be formed by using a mold, wherein the mold includes a plurality of pillars corresponding to the connection pads on the substrate 300a. After the encapsulant material is filled and hardened, the encapsulant 318 is formed with a plurality of openings therein and the connection pads on the substrate 300a are exposed by the openings. Then, a conductive material is fill into the openings, and the electrical connection devices are respectively formed in the openings to connect with the exposed connection pads on the substrate 300a. In the other embodiment of the present invention, an encapsulant material layer is firstly formed on the substrate 300a by, for example, a molding or coating method. Then, the encapsulant material layer is drilled to form a plurality of openings in the encapsulant material layer, wherein the openings expose the connection pads on the substrate 300a. Subsequently, a conductive material is fill into the openings, and the electrical connection devices are respectively formed in the openings to connect with the exposed connection pads on the substrate 300a.
According to the aforementioned exemplary embodiments, it is known that a greater portion of the room between the substrates of the two chip package structures has been filled with encapsulant materials, so that the room between the two chip package structures is greatly decreased. Accordingly, in the stack process of the two chip package structures, the warpage can be prevented from occurring in the chip package structures, to avoid cold joint from arising between the chip package structures.
Each stacked package structures disclosed in the aforementioned embodiments is a two-chip stacked package structure, however, it should be noted that the stacked package structure of the present invention may be a stacked package structure including more than two chips, and the present invention is not limited thereto.
According to the aforementioned description, one advantage of the present invention is that the application of the present stacked package structure can decrease the area of the package structure, so the area of the printed circuit board can be greatly reduced.
According to the aforementioned description, another advantage of the present invention is that the application of the present method can integrate the connection between an upper chip package structure and a bottom chip package structure, effectively avoid the warpage from occurring, prevent a cold joint condition from arising between two chip package structures, and greatly enhance the yield of the stacked package process.
As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.
Claims
1. A method for manufacturing a stacked package structure, comprising:
- forming a first chip package structure, comprising:
- providing a first chip carrier having a first surface and a second surface in opposition to each other;
- forming a plurality of bonding wires on the first surface of the first chip carrier;
- providing at least one first chip on and electrically connected to the first surface of the first chip carrier, wherein each bonding wire is higher than the at least one first chip in altitude; and
- forming an encapsulant covering the first surface of the first chip carrier, the at least one first chip and the bonding wires, wherein at least one top end of each bonding wire is exposed at a surface of the encapsulant; and
- providing a second chip package structure electrically connected to and stacked on the first chip package structure.
2. The method for manufacturing a stacked package structure according to claim 1, wherein before providing the second chip package structure, forming a plurality of first electrical connections respectively deposed on the top end of each bonding wire, so that the second chip package structure is electrically connected to the first chip package structure via the first electrical connections.
3. The method for manufacturing a stacked package structure according to claim 1, wherein the step of forming the encapsulant comprises:
- providing an encapsulant material layer to cover the first surface of the first chip carrier, the at least one first chip and the bonding wires; and
- performing a grinding step to remove a portion of the encapsulant material layer, until the top end of each bonding wire is exposed.
4. The method for manufacturing a stacked package structure according to claim 3, wherein the grinding step is a mechanical grinding step or a chemical grinding step.
5. The method for manufacturing a stacked package structure according to claim 2, wherein the step of forming the first chip package structure further comprises forming a plurality of second electrical connections respectively deposed on the second surface of the first chip carrier.
6. The method for manufacturing a stacked package structure according to claim 1, wherein a material of the bonding wires is selected from the group consisting of Cu, Al, Au, Sn and an alloy thereof.
7. The method for manufacturing a stacked package structure according to claim 2, wherein the step of forming the first electrical connections is performed by a direct ball attach method, a screen print method, an electro plating method or an electroless plating method.
8. The method for manufacturing a stacked package structure according to claim 1, wherein before the step of forming the encapsulant, the step of forming the first chip package structure further comprises forming at least one passive device on the first surface of the first chip carrier.
9. The method for manufacturing a stacked package structure according to claim 1, wherein the step of providing the second chip structure comprises:
- providing a second chip carrier having a first surface and a second surface in opposition to each other;
- forming a plurality of electrical connection devices on the first surface of the second chip carrier;
- providing at least one second chip on and electrically connected to the first surface of the second chip carrier, wherein each electrical connection device is higher than the at least one second chip in altitude; and
- forming another encapsulant covering the first surface of the second chip carrier, the at least one second chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the another encapsulant.
10. The method for manufacturing a stacked package structure according to claim 9, wherein the step of forming the another encapsulant comprises:
- providing an encapsulant material layer to cover the first surface of the second chip carrier, the at least one second chip and the electrical connection devices; and
- performing a grinding step to remove a portion of the encapsulant material layer, until the top end of each electrical connection device is exposed.
11. The method for manufacturing a stacked package structure according to claim 9, wherein the electrical connection devices are selected from the group consisting of bonding wires, conductive studs, pins, electronic components and any combination thereof.
12. The method for manufacturing a stacked package structure according to claim 1, wherein the chip carrier is a substrate or a leadframe.
13. The method for manufacturing a stacked package structure according to claim 2, wherein the first electrical connections are connection bumps or balls.
Type: Application
Filed: Jun 28, 2007
Publication Date: Nov 1, 2007
Applicant:
Inventor: Yonggill Lee (Kaohsiung)
Application Number: 11/819,624
International Classification: H01L 21/00 (20060101);