Abstract: The present invention relates to a movement average filter based on charge sampling and a moving average filtering method using the same. The moving average filter includes a voltage-current converter and a first sampling unit. The voltage-current converter converts an input voltage signal into an input current signal and outputs the input current signal. The first sampling unit includes a first 1-unit sampler, an ?-unit sampler, and a second 1-unit sampler connected in parallel between an output terminal of the voltage-current converter and a filtered signal output terminal, wherein each of the first 1-unit sampler, the ?-unit sampler, and the second 1-unit sampler has a sampling capacitor bank for performing charge sampling. A ratio of sampling capacitances of sampling capacitor banks of the first 1-unit sampler, the ?-unit sampler, and the second 1-unit sampler is 1:?:1, wherein a is adjusted to have a value between 1 and 2.

Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Abstract: A cognitive radio (CR) communication apparatus and method is provided. A cognitive radio (CR) communication apparatus includes a signal receiving unit which receives signals from a primary user of a primary system and a secondary transmitter of a secondary system, the received signals including an element associated with at least one known signal of the secondary transmitter, and a determination unit which determines whether a signal of the primary user exists from among the received signals based on the element associated with the at least one known signal.

Abstract: A cognitive radio (CR) communication apparatus and method is provided. A cognitive radio (CR) communication apparatus includes a signal receiving unit which receives signals from a primary user of a primary system and a secondary transmitter of a secondary system, the received signals including an element associated with at least one known signal of the secondary transmitter, and a determination unit which determines whether a signal of the primary user exists from among the received signals based on the element associated with the at least one known signal.

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract: A wordline driver includes a pre-driver, a sub-wordline driver and a transmission circuit. The pre-driver generates a wordline enable signal and a wordline disable signal based on one or more selection signals, a decoded address signal, and one or more timing control signals. The transmission circuit transmits the wordline enable signal and the wordline disable signal. The sub-wordline driver controls a voltage level of the sub-wordline based on the wordline enable signal and the wordline disable signal that are transmitted by the transmission circuit. Therefore, driving capacity may be improved.

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract: A low density parity code (LDPC) encoding and decoding devices and encoding and decoding methods thereof are provided. An LDPC encoding device includes an information obtaining unit which obtains status information of at least two frequency bands, a matrix generation unit which generates a parity check matrix based on the status information, the parity check matrix including sub matrices which correspond to the at least two frequency bands, and an encoder which generates data bits and parity bits using an LDPC with the generated parity check matrix.

Abstract: A semiconductor device includes a comparator, an internal voltage generator, a control signal generator, and a selector. The comparator may compare a reference voltage to an internal voltage and output a comparison signal. The internal voltage generator may generate and output the internal voltage in response to the comparison signal. The control signal generator may generate a control signal. The selector may receive first and second target voltages, and select and output one of the first and second target voltages as the reference voltage in response to the control signal.

Abstract: A semiconductor memory device comprises a memory cell configured to output data to a pair of bitlines, a variable delay circuit configured to receive a sense amplifier enable signal, adjust a delay of the sense amplifier enable signal by changing a slope of a delay based on a variable external power supply voltage, and output a delayed sense amplifier enable signal, and a bitline sense amplifier configured to amplify a voltage difference between the pair of bitlines in response to the delayed sense amplifier enable signal and output the amplified voltage difference to a pair of input/output lines.

Abstract: An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

Abstract: An interference determination apparatus, including a signal receiver to receive a first signal of a primary network and a second signal of a secondary network; a correlator to compute a correlation value of a first cyclic prefix included in the first signal and a correlation value of a second cyclic prefix included in the second signal; and an interference determination unit to determine an interference level or whether the interference occurs between the primary network and the secondary network, using the correlation value of the first cyclic prefix and the correlation value of the second cyclic prefix.

Abstract: A video unified codec device and corresponding video method. The unified codec device includes parsing and decoding functional units (PD FUs) extracting and grouping context information, control signals, and data in bit streams inputted according to different syntax data per codec, macro-block-based functional units (MB-based FUs) comprising block-based process units of each codec, for decoding data outputted from PD FUs, and a global control unit (GCU) for controlling MB-based FUs grouped after corresponding control signals and context information received from PD FUs to each codec and processing.

Abstract: An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

Abstract: An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

Abstract: A block decoding circuit of a semiconductor memory device includes a plurality of block decoders, a plurality of repair address check circuits, a dummy repair address check circuit and a block selection signal generation circuit. The plurality of block decoders are configured to decode a received block selection address. The plurality of repair address check circuits are configured to generate second output signals based on whether a received block selection address and word line selection address are repair addresses. The dummy repair address check circuit is configured to generate a control signal in response to the block selection address and the word line selection address. The block selection signal generation circuit is configured to generate block selection signals based on the first output signals from the plurality of block decoders, the control signal from the dummy repair address circuit, and the second output signals from the repair address check circuits.

Abstract: A method of assigning and managing reference signals in a multi-cell environment, and a network device and a terminal for applying the method, are provided. Reference signal patterns may be assigned to multiple femtocells through a long term coordination of a central control unit that is used to control multiple cells.

Abstract: There are provided selective prediction encoding and decoding methods and selective prediction encoding and decoding devices. The selective prediction encoding device selects and performs one of an AC/DC prediction encoding method and an intra prediction encoding method which corresponds to the smaller of code amount from AC/DC prediction and an amount of AVC intra coding, records information indicating the selected encoding method in a header of a bit stream, and transmits the bit stream to the selective prediction decoding device. The selective prediction decoding device decodes the transmitted bit stream by the use of a decoding process corresponding to the information recorded in the header. Accordingly, it is possible to improve compression ratio and image quality by using the selective prediction encoding and decoding methods.

Abstract: A wordline driver includes a pre-driver, a sub-wordline driver and a transmission circuit. The pre-driver generates a wordline enable signal and a wordline disable signal based on one or more selection signals, a decoded address signal, and one or more timing control signals. The transmission circuit transmits the wordline enable signal and the wordline disable signal. The sub-wordline driver controls a voltage level of the sub-wordline based on the wordline enable signal and the wordline disable signal that are transmitted by the transmission circuit. Therefore, driving capacity may be improved.