Abstract: A semiconductor memory device comprises a memory cell configured to output data to a pair of bitlines, a variable delay circuit configured to receive a sense amplifier enable signal, adjust a delay of the sense amplifier enable signal by changing a slope of a delay based on a variable external power supply voltage, and output a delayed sense amplifier enable signal, and a bitline sense amplifier configured to amplify a voltage difference between the pair of bitlines in response to the delayed sense amplifier enable signal and output the amplified voltage difference to a pair of input/output lines.

Abstract: A semiconductor memory device includes a command buffer that receives an external command and outputs a first command signal, a clock buffer that receives an external clock signal and outputs a first internal clock signal, a delay measurement and initialization unit that receives the first internal clock signal and a fourth internal clock signal and responsively outputs a second internal clock signal and a plurality of delayed signals corresponding to a delay time between when the external clock signal is input and data is output, a delay locked loop that receives the second internal clock signal and outputs a third internal clock signal and the fourth internal clock signal, a latency signal generation unit that delays the first command signal by a delay time between when the second internal clock signal is input to the delay locked loop and when the third internal clock signal is output from the delay locked loop, and then outputs the delayed first command signal as a latency signal, in response to the secon

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract: A semiconductor device includes a comparator, an internal voltage generator, a control signal generator, and a selector. The comparator may compare a reference voltage to an internal voltage and output a comparison signal. The internal voltage generator may generate and output the internal voltage in response to the comparison signal. The control signal generator may generate a control signal. The selector may receive first and second target voltages, and select and output one of the first and second target voltages as the reference voltage in response to the control signal.

Abstract: Provided are a method and apparatus for controlling a read latency of a high-speed DRAM. A memory device may include a delay measurement unit, a delay locked loop, a latency counter and a data output buffer. The delay measurement unit measures a delay time between when an external clock signal is input and when read data is output to generate measurement signals and generates a first internal clock signal delayed from the external clock signal. The delay locked loop (DLL) receives the first internal clock signal and generates a second internal clock signal synchronized with the external clock signal. The latency counter generates a latency signal from an external read command signal in response to the measurement signals, and the data output buffer outputs the read data in response to the latency signal and the second internal clock signal.

Abstract: Disclosed herein are an electrode connector including a conductive wire and a plurality of plates mounted on the wire such that the plates can be electrically connected to electrodes of cells, wherein the plates are electrically connected to the wire in a structure in which the plates are coupled to the wire by clamping, and a surface (A) of each plate contacting the wire is plated with the same metal (a) as the wire while a surface (B) of each plate connected to the corresponding electrode of each cell is plated with the same metal (b) as the corresponding electrode of each cell, and a battery module constructed with the electrode connector.

Abstract: An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

Abstract: An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

Abstract: Disclosed herein is a method of manufacturing a battery core pack having a plurality of unit cells, especially a plurality of cylindrical batteries, which are connected with each other by connecting members. According to the present invention, the structure of the battery core pack can be easily modified by merely changing the combination of the connecting members without manufacturing additional connecting members. Consequently, common use of the connecting members is possible.

Abstract: A low density parity code (LDPC) encoding and decoding devices and encoding and decoding methods thereof are provided. An LDPC encoding device includes an information obtaining unit which obtains status information of at least two frequency bands, a matrix generation unit which generates a parity check matrix based on the status information, the parity check matrix including sub matrices which correspond to the at least two frequency bands, and an encoder which generates data bits and parity bits using an LDPC with the generated parity check matrix.

Abstract: A cognitive radio (CR) communication apparatus and method is provided. A cognitive radio (CR) communication apparatus includes a signal receiving unit which receives signals from a primary user of a primary system and a secondary transmitter of a secondary system, the received signals including an element associated with at least one known signal of the secondary transmitter, and a determination unit which determines whether a signal of the primary user exists from among the received signals based on the element associated with the at least one known signal.

Abstract: A method and apparatus for controlling a power-down mode of a delay locked loop (DLL), in which the apparatus includes a first switch unit, a DLL, and a second switch unit. The first switch unit transfers a first clock signal in response to a clock input enable signal. The DLL receives the first clock signal through the first switch unit to generate a second clock signal and is turned off by a power-down signal that is generated from the first clock signal latched by the first switch unit. The second switch unit transfers the second clock signal in response to a clock output enable signal. In a power-down mode, the clock input enable signal is deactivated in response to a clock enable signal and the clock output enable signal is deactivated after a predetermined number of clock cycles that are necessary for the latched first clock signal to be completely transferred through the delay cells of the DLL to an output terminal of the DLL.

Abstract: Disclosed herein are a safety device for secondary batteries that is capable of pressing a piezoelectric element using a seesaw member, which is constructed in a variable fixing structure, to generate electric current when a battery cell swells due to the abnormal operation or the degradation of the battery, and controlling the operation of the battery according to the generated electric current using a protection circuit module, thereby securing the safety of the battery, and a battery pack including a battery cell, which has low mechanical strength and high deformability, mounted in a frame member having the safety device, whereby the safety of the battery is improved and the assembly efficiency of the battery pack is improved.

Abstract: A block decoding circuit of a semiconductor memory device includes a plurality of block decoders, a plurality of repair address check circuits, a dummy repair address check circuit and a block selection signal generation circuit. The plurality of block decoders are configured to decode a received block selection address. The plurality of repair address check circuits are configured to generate second output signals based on whether a received block selection address and word line selection address are repair addresses. The dummy repair address check circuit is configured to generate a control signal in response to the block selection address and the word line selection address. The block selection signal generation circuit is configured to generate block selection signals based on the first output signals from the plurality of block decoders, the control signal from the dummy repair address circuit, and the second output signals from the repair address check circuits.

Abstract: A semiconductor memory device includes a command buffer that receives an external command and outputs a first command signal, a clock buffer that receives an external clock signal and outputs a first internal clock signal, a delay measurement and initialization unit that receives the first internal clock signal and a fourth internal clock signal and responsively outputs a second internal clock signal and a plurality of delayed signals corresponding to a delay time between when the external clock signal is input and data is output, a delay locked loop that receives the second internal clock signal and outputs a third internal clock signal and the fourth internal clock signal, a latency signal generation unit that delays the first command signal by a delay time between when the second internal clock signal is input to the delay locked loop and when the third internal clock signal is output from the delay locked loop, and then outputs the delayed first command signal as a latency signal, in response to the secon

Abstract: An interference determination apparatus, including a signal receiver to receive a first signal of a primary network and a second signal of a secondary network; a correlator to compute a correlation value of a first cyclic prefix included in the first signal and a correlation value of a second cyclic prefix included in the second signal; and an interference determination unit to determine an interference level or whether the interference occurs between the primary network and the secondary network, using the correlation value of the first cyclic prefix and the correlation value of the second cyclic prefix.

Abstract: A method and apparatus for controlling a power-down mode of a delay locked loop (DLL), in which the apparatus includes a first switch unit, a DLL, and a second switch unit. The first switch unit transfers a first clock signal in response to a clock input enable signal. The DLL receives the first clock signal through the first switch unit to generate a second clock signal and is turned off by a power-down signal that is generated from the first clock signal latched by the first switch unit. The second switch unit transfers the second clock signal in response to a clock output enable signal. In a power-down mode, the clock input enable signal is deactivated in response to a clock enable signal and the clock output enable signal is deactivated after a predetermined number of clock cycles that are necessary for the latched first clock signal to be completely transferred through the delay cells of the DLL to an output terminal of the DLL.

Abstract: Provided are a method and apparatus for controlling a read latency of a high-speed DRAM. A memory device may include a delay measurement unit, a delay locked loop, a latency counter and a data output buffer. The delay measurement unit measures a delay time between when an external clock signal is input and when read data is output to generate measurement signals and generates a first internal clock signal delayed from the external clock signal. The delay locked loop (DLL) receives the first internal clock signal and generates a second internal clock signal synchronized with the external clock signal. The latency counter generates a latency signal from an external read command signal in response to the measurement signals, and the data output buffer outputs the read data in response to the latency signal and the second internal clock signal.

Abstract: The present invention is directed to a video unified codec device and its method. According to an embodiment of this invention, the unified codec device comprises parsing and decoding functional units (PD FUs) extracting and grouping context information, control signals, and data in bit streams inputted according to different syntax data per codec, macro-block-based functional units (MB-based FUs) unified based on block-based process units of each codec, for decoding data outputted from PD FUs, and a global control unit (GCU) for controlling MB-based FUs grouped after corresponding control signals and context information received from PD FUs to each codec and processing. By this invention, a new concept and structure of unified codec corresponding to similarities, differences, and considerations between different codecs can be presented.

Abstract: Disclosed herein are an electrode connector including a conductive wire and a plurality of plates mounted on the wire such that the plates can be electrically connected to electrodes of cells, wherein the plates are electrically connected to the wire in a structure in which the plates are coupled to the wire by clamping, and a surface (A) of each plate contacting the wire is plated with the same metal (a) as the wire while a surface (B) of each plate connected to the corresponding electrode of each cell is plated with the same metal (b) as the corresponding electrode of each cell, and a battery module constructed with the electrode connector.