Patents by Inventor Yong-Hoon Son

Yong-Hoon Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080217689
    Abstract: Semiconductor devices are provided including gate patterns on a substrate and isolation regions on the substrate. Insulating patterns are provided in the substrate below the gate patterns. Source/drain regions are provided in the substrate. Related methods of fabricating semiconductor devices are also provided.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 11, 2008
    Inventors: Yong-Hoon Son, Hye-Ran Choi, Jong-Wook Lee
  • Publication number: 20080217616
    Abstract: A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 11, 2008
    Inventors: Yong-hoon Son, Si-young Choi, Jong-wook Lee
  • Patent number: 7422965
    Abstract: A method of fabricating a transistor device includes forming a non-crystalline germanium layer on a seed layer. The non-crystalline germanium layer is selectively locally heated to about a melting point thereof to form a single-crystalline germanium layer on the seed layer. The non-crystalline germanium layer may be selectively locally heated, for example, by applying a laser to a portion of the non-crystalline germanium layer. Related devices are also discussed.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: September 9, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee
  • Publication number: 20080194083
    Abstract: In a method of manufacturing a semiconductor device, a string structure including a selection transistor and a memory cell on a substrate. An insulation layer pattern is formed on the substrate to cover the string structure. The insulation layer pattern includes at least one opening exposing a portion of the substrate adjacent to the selection transistor. A seed layer including a single-crystalline material is formed in the opening. An amorphous thin film including an amorphous material is formed on the insulation layer pattern and the seed layer. The amorphous thin film is transformed into a single-crystalline thin film, using the single-crystalline material in the seed layer as a seed during a phase transition of the amorphous thin film, to form a channel layer on the insulation layer pattern and the seed layer. Therefore, the semiconductor device including the channel layer having the single-crystalline thin film may be manufactured.
    Type: Application
    Filed: April 2, 2008
    Publication date: August 14, 2008
    Inventors: Yong-Hoon Son, Si-Young Choi, Jong-Wook Lee, Pil-Kyu Kang
  • Publication number: 20080179665
    Abstract: A memory cell transistor includes a semiconductor substrate having a first impurity region of first conductivity type (e.g., N-type) therein. A U-shaped semiconductor layer having a second impurity region of first conductivity type therein is provided on the first impurity region. A gate insulating layer is provided, which lines a bottom and an inner sidewall of the U-shaped semiconductor layer. A gate electrode is provided on the gate insulating layer. The gate electrode is surrounded by the inner sidewall of the U-shaped semiconductor layer. A word line is provided, which is electrically coupled to the gate electrode, and a bit line is provided, which is electrically coupled to the second impurity region.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 31, 2008
    Inventors: Jong-Wook Lee, Yong-Hoon Son, Si-Young Choi
  • Patent number: 7396761
    Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure located on a substrate. The plug and the channel structure comprise a material in a single crystalline state that is changed from an amorphous state by an irradiation of a laser beam. The channel structure is doped with impurities such as boron, phosphorus or arsenic.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: July 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Kwan Kang, Jong-Wook Lee, Yong-Hoon Son, Yu-Gyun Shin, Jun-Ho Lee
  • Publication number: 20080157095
    Abstract: Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.
    Type: Application
    Filed: March 11, 2008
    Publication date: July 3, 2008
    Inventors: Yong-Hoon Son, Yu-Gyun Shin
  • Patent number: 7394117
    Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: July 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Soo Jung, Deok-Hyung Lee, Si-Young Choi, Byeong-Chan Lee, Yong-Hoon Son
  • Publication number: 20080116487
    Abstract: Transistors having a high carrier mobility and devices incorporating the same are fabricated by forming a preliminary semiconductor layer in a semiconductor substrate at both sides of a gate pattern. A source/ drain semiconductor layer having a heterojunction with the semiconductor substrate is formed by irradiating a laser beam onto the preliminary semiconductor layer. The source/drain semiconductor layer is formed in a recrystallized single crystal structure.
    Type: Application
    Filed: July 24, 2007
    Publication date: May 22, 2008
    Inventors: Byeong-Chan Lee, Si-Young Choi, Young-Pil Kim, Yong-Hoon Son, In-Soo Jung, Jin-Bum Kim
  • Patent number: 7364955
    Abstract: Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: April 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Yu-Gyun Shin
  • Patent number: 7364990
    Abstract: First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: April 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee
  • Publication number: 20080093601
    Abstract: Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.
    Type: Application
    Filed: October 12, 2007
    Publication date: April 24, 2008
    Inventors: Pil-Kyu Kang, Yong-Hoon Son, Si-Young Choi, Jong-Wook Lee, Byeong-Chan Lee, In-Soo Jung
  • Publication number: 20080070372
    Abstract: In a method of manufacturing a semiconductor device, an insulating layer pattern defining at least one opening partially exposing a semiconductor substrate is formed on a semiconductor substrate including a single crystalline material. An amorphous thin layer is formed on the insulating layer pattern to fill up the opening. The amorphous thin layer is transformed into a single crystalline thin layer by providing the amorphous thin layer with a laser beam having sufficient energy to melt the amorphous thin layer. Here, the semiconductor substrate partially exposed through the opening is used as a seed. A gate pattern is formed on the single crystalline thin layer. Source/drain regions are formed at surface portions of the single crystalline thin layer adjacent to both sidewalls of the gate pattern.
    Type: Application
    Filed: September 10, 2007
    Publication date: March 20, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Hoon SON, Si-Young CHOI, Jong-Wook LEE
  • Patent number: 7320908
    Abstract: Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor and the sidewall of the trench and a spacer is formed on the insulating layer such that the spacer is on the sidewall of the trench and on a portion of the floor of the trench. The insulating layer is removed on the floor of the trench and beneath the spacer such that a portion of the floor of the trench is at least partially exposed, the spacer is spaced apart from the floor of the trench and a portion of the preliminary active pattern is partially exposed. A portion of the exposed portion of the preliminary active pattern is partially removed to provide an active pattern that defines a recessed portion beneath the spacer. A buried insulating layer is formed in the recessed portion of the active pattern. Related devices are also provided.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: January 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Si-Young Choi, Byeong-Chan Lee, Jong-Wook Lee, In-Soo Jung, Deok-Hyung Lee
  • Publication number: 20080014726
    Abstract: Methods of fabricating a semiconductor device are provided. A semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A thin layer is formed on the semiconductor substrate. The thin layer is patterned to form a plurality of spaced apart field structures and to expose therebetween portions of the semiconductor substrate having the single crystalline structure. A non-crystalline layer is formed on the exposed portions of the semiconductor substrate having the single crystalline structure. The non-crystalline layer is planarized to expose upper surfaces of the field structures and define non-crystalline active structures from the non-crystalline layer between the field structures. A laser beam is generated that heats the non-crystalline active structures to change them into single crystalline active structures having substantially the same single crystalline structure as the defined region of the semiconductor substrate.
    Type: Application
    Filed: February 2, 2007
    Publication date: January 17, 2008
    Inventors: Yong-Won Cha, Sung-Kwan Kang, Pil-Kyu Kang, Yong-Hoon Son, Jong-Wook Lee
  • Publication number: 20070231976
    Abstract: A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 4, 2007
    Inventors: Sung-Kwan Kang, Yu-Gyun Shin, Jong-Wook Lee, Yong-Hoon Son
  • Publication number: 20070224789
    Abstract: In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor substrate with an opening that exposes a portion of the defined region of the semiconductor substrate having the single crystalline structure. A first non-single crystalline film is formed on the exposed portion of the semiconductor substrate and that at least substantially fills the opening in the first insulating film. A laser beam is generated that heats the first non-single crystalline film to change the first non-single crystalline film into a first single crystalline film having substantially the same single crystalline structure as the defined region of the semiconductor substrate.
    Type: Application
    Filed: March 12, 2007
    Publication date: September 27, 2007
    Inventors: Sungkwan Kang, Yong-Hoon Son, Jongwook Lee, Yugyun Shin
  • Publication number: 20070218607
    Abstract: In a method of forming a single crystalline semiconductor layer, an amorphous layer may be formed on a seed layer that includes a single crystalline material. The single crystalline layer may be formed from the amorphous layer by irradiating a laser beam onto the amorphous layer using the seed layer as a seed for a phase change of the amorphous layer. The laser beam may have an energy for melting the amorphous layer, and the laser beam may be irradiated onto the amorphous layer without generating a superimposedly irradiated region of the amorphous layer. The single crystalline layer may include a high density of large-sized grains without generating a protrusion thereon through a simple process so that a semiconductor device including the single crystalline layer may have a high degree of integration and improved electrical characteristics.
    Type: Application
    Filed: May 22, 2007
    Publication date: September 20, 2007
    Inventors: Yong-Hoon Son, Si-Young Choi, Jong-Wook Lee
  • Publication number: 20070190732
    Abstract: A method of forming a semiconductor device may include forming a fin structure extending from a substrate. The fin structure may include first and second source/drain regions and a channel region therebetween, and the first and second source/drain regions may extend a greater distance from the substrate than the channel region. A gate insulating layer may be formed on the channel region, and a gate electrode may be formed on the gate insulating layer so that the gate insulating layer is between the gate electrode and the channel region. Related devices are also discussed.
    Type: Application
    Filed: March 27, 2007
    Publication date: August 16, 2007
    Inventors: Deok-Hyung Lee, Si-Young Choi, Byeong-Chan Lee, Yong-Hoon Son, In-Soo Jung
  • Publication number: 20070163489
    Abstract: A method of forming a layer, including forming an insulation layer having an opening on a single crystalline substrate, the opening partially exposing an upper face of the substrate, forming a first seed layer in the opening, converting an upper portion of the first seed layer to a first amorphous layer, converting the first amorphous layer to a second seed layer, forming a second amorphous layer on the second seed layer, and converting the second amorphous layer to a single crystalline layer.
    Type: Application
    Filed: January 12, 2007
    Publication date: July 19, 2007
    Inventors: Yong-Hoon Son, Jong-Wook Lee