Patents by Inventor Yong Hwan Noh
Yong Hwan Noh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240067535Abstract: A water purifier includes: a filter module for providing purified water by filtering raw water; a fitting valve module detachably fastened to the filter module to provide at least one of a flow path for a flow of raw water supplied to the filter module and a flow path for a flow of the purified water discharged from the filter module; and a frame including a valve support for movably supporting the fitting valve module to be movable. The fitting valve module is selectively placed in a separated state in which the fitting valve module is separated from the filter module by moving in a direction away from the filter module, or a coupled state in which the fitting valve module coupled to the filter module by moving toward the filter module.Type: ApplicationFiled: December 30, 2021Publication date: February 29, 2024Applicant: COWAY CO., LTD.Inventors: Ki Hong MIN, Man Uk PARK, Yong Yeon NOH, Dae Hwan KIM, Doo Won HAN
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Patent number: 8030958Abstract: A system for providing a reference voltage includes a tester adapted to provide a predetermined current, a first ground pad connected to a ground voltage of the tester, a second ground pad connected between the tester and the first ground pad, the second ground pad being connected to the tester through first and second resistors, a reference voltage pad connected to a node between the first and second resistors, the reference voltage pad adapted to provide a test reference voltage, and a multiplexer connected to the reference voltage pad, the multiplexer configured to output the test reference voltage as a reference voltage during substantial voltage variation.Type: GrantFiled: July 25, 2007Date of Patent: October 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Yong-hwan Noh
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Patent number: 7902871Abstract: Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.Type: GrantFiled: April 13, 2010Date of Patent: March 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hwan Noh, Chul-Sung Park
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Patent number: 7801052Abstract: A transmission delay measuring circuit may include a first transmission path, a second transmission path, an inversion circuit, a first multiplexer, and an output terminal. The second transmission path may have the same structure as the structure of the first transmission path and may receive the output of the first transmission path. The inversion circuit may invert the output of the second transmission path. The first multiplexer may output one of the external input signal and an inverted output of the second transmission path to the first transmission path in response to a test mode enable signal. The output terminal may output, as a measuring signal, a signal in an arbitrary node of a closed loop formed of the first transmission path, the second transmission path, the inversion circuit, and the first multiplexer. The transmission delay measuring apparatus may more accurately measure the transmission delay of a transmission path in a semiconductor device in a die-to-die wafer state or a package state.Type: GrantFiled: September 28, 2007Date of Patent: September 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Yong-hwan Noh
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Publication number: 20100194433Abstract: Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.Type: ApplicationFiled: April 13, 2010Publication date: August 5, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hwan NOH, Chul-Sung PARK
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Publication number: 20090045844Abstract: Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.Type: ApplicationFiled: August 14, 2008Publication date: February 19, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hwan NOH, Chul-Sung PARK
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Publication number: 20080175082Abstract: A serial power capacitor device is provided which includes a noise suppressing circuit which includes a plurality of capacitive elements for suppressing a power noise, and a stabilizing circuit which stabilizes an operation of the noise suppressing circuit by compensating for variations in leakage current of the capacitive elements. The plurality of capacitive elements may, for example, be a plurality of power capacitors connected in series between a power source voltage and a ground voltage, and the stabilizing circuit may, for example, include a plurality of resistors connected in series between the power source voltage and the ground voltage. The resistors may, for example, be connected in parallel to the respective power capacitors, and a resistive value of each of the resistors may, for example, be less than an intrinsic resistive value of the power capacitors, respectively. The capacitive elements may, for example, be formed by DRAM cells or by metal oxide semiconductor (MOS) transistors.Type: ApplicationFiled: January 23, 2008Publication date: July 24, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yong-Hwan NOH
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Publication number: 20080150615Abstract: A system for providing a reference voltage includes a tester adapted to provide a predetermined current, a first ground pad connected to a ground voltage of the tester, a second ground pad connected between the tester and the first ground pad, the second ground pad being connected to the tester through first and second resistors, a reference voltage pad connected to a node between the first and second resistors, the reference voltage pad adapted to provide a test reference voltage, and a multiplexer connected to the reference voltage pad, the multiplexer configured to output the test reference voltage as a reference voltage during substantial voltage variation.Type: ApplicationFiled: July 25, 2007Publication date: June 26, 2008Inventor: Yong-hwan Noh
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Publication number: 20080101249Abstract: A transmission delay measuring circuit may include a first transmission path, a second transmission path, an inversion circuit, a first multiplexer, and an output terminal. The second transmission path may have the same structure as the structure of the first transmission path and may receive the output of the first transmission path. The inversion circuit may invert the output of the second transmission path. The first multiplexer may output one of the external input signal and an inverted output of the second transmission path to the first transmission path in response to a test mode enable signal. The output terminal may output, as a measuring signal, a signal in an arbitrary node of a closed loop formed of the first transmission path, the second transmission path, the inversion circuit, and the first multiplexer. The transmission delay measuring apparatus may more accurately measure the transmission delay of a transmission path in a semiconductor device in a die-to-die wafer state or a package state.Type: ApplicationFiled: September 28, 2007Publication date: May 1, 2008Inventor: Yong-hwan Noh
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Patent number: 7151710Abstract: The invention is directed to data input/output organization system and method in a semiconductor memory device. The memory device has a plurality of memory arrays, in one embodiment, an odd number of memory arrays. The arrays are divided into blocks, and the blocks are divided into segments. A control circuit provides control signals to the memory arrays such that data is input and/or output to and from the memory device in multiples of nine bits. The data bits are input or output simultaneously without the need for multiplexing circuitry. This results in reduced power consumption and increased memory processing speed.Type: GrantFiled: May 6, 2005Date of Patent: December 19, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Hyang Ja Yang, Yong Hwan Noh, Yun Jin Cho, Chul Sung Park
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Patent number: 7068058Abstract: Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.Type: GrantFiled: October 30, 2004Date of Patent: June 27, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-Sung Park, Yong-Hwan Noh, Byong-Kwon Lee, Hyang-Ja Yang
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Patent number: 6958947Abstract: A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.Type: GrantFiled: February 6, 2003Date of Patent: October 25, 2005Assignee: Samsung Electronics Co., LTDInventors: Chul-Sung Park, Hyang-Ja Yang, Seung-Min Lee, Yong-Hwan Noh
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Patent number: 6949960Abstract: An integrated circuit device includes a pin for receiving a DC voltage component signal. The device includes a signal source for applying an AC signal to the pin, a buffer for converting the AC signal into a digital signal, and a digital detector for detecting a frequency of the digital signal and outputting a predetermined detection signal. The predetermined detection signal is activated when the frequency of the digital signal is greater than or equal to a predetermined frequency. The predetermined detection signal is used as a signal for setting predetermined functional modes. The device further includes registers or a differential amplifier and a decoder for generating a plurality of functional mode signals.Type: GrantFiled: August 6, 2003Date of Patent: September 27, 2005Assignee: Samsung Electronics, Co., Ltd.Inventors: Chul-Sung Park, Hyang-Ja Yang, Hong-Kyun Kim, Yong-Hwan Noh
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Publication number: 20050201184Abstract: The invention is directed to data input/output organization system and method in a semiconductor memory device. The memory device has a plurality of memory arrays, in one embodiment, an odd number of memory arrays. The arrays are divided into blocks, and the blocks are divided into segments. A control circuit provides control signals to the memory arrays such that data is input and/or output to and from the memory device in multiples of nine bits. The data bits are input or output simultaneously without the need for multiplexing circuitry. This results in reduced power consumption and increased memory processing speed.Type: ApplicationFiled: May 6, 2005Publication date: September 15, 2005Inventors: Hyang Yang, Yong Hwan Noh, Yun Cho, Chul Park
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Patent number: 6909661Abstract: The invention is directed to data input/output organization system and method in a semiconductor memory device. The memory device has a plurality of memory arrays, in one embodiment, an odd number of memory arrays. The arrays are divided into blocks, and the blocks are divided into segments. A control circuit provides control signals to the memory arrays such that data is input and/or output to and from the memory device in multiples of nine bits. The data bits are input or output simultaneously without the need for multiplexing circuitry. This results in reduced power consumption and increased memory processing speed.Type: GrantFiled: June 23, 2003Date of Patent: June 21, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Hyang Ja Yang, Yong Hwan Noh, Yun Jin Cho, Chul Sung Park
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Publication number: 20050056834Abstract: Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.Type: ApplicationFiled: October 30, 2004Publication date: March 17, 2005Inventors: Chul-Sung Park, Yong-Hwan Noh, Byong-Kwon Lee, Hyang-Ja Yang
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Patent number: 6822330Abstract: Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.Type: GrantFiled: January 16, 2003Date of Patent: November 23, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-Sung Park, Yong-Hwan Noh, Byong-Kwon Lee, Hyang-Ja Yang
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Publication number: 20040032915Abstract: An integrated circuit device comprises a pin for receiving a DC voltage component signal. The device comprises a signal source for applying an AC signal to the pin, a buffer for converting the AC signal into a digital signal, and a digital detector for detecting a frequency of the digital signal and outputting a predetermined detection signal. The predetermined detection signal is activated when the frequency of the digital signal is greater than or equal to a predetermined frequency. The predetermined detection signal is used as a signal for setting predetermined functional modes. The device further comprises registers or a differential amplifier and a decoder for generating a plurality of functional mode signals.Type: ApplicationFiled: August 6, 2003Publication date: February 19, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Chul-Sung Park, Hyang-Ja Yang, Hong-Kyun Kim, Yong-Hwan Noh
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Publication number: 20040022115Abstract: A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.Type: ApplicationFiled: February 6, 2003Publication date: February 5, 2004Inventors: Chul-Sung Park, Hyang-Ja Yang, Seung-Min Lee, Yong-Hwan Noh
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Publication number: 20040016975Abstract: The invention is directed to data input/output organization system and method in a semiconductor memory device. The memory device has a plurality of memory arrays, in one embodiment, an odd number of memory arrays. The arrays are divided into blocks, and the blocks are divided into segments. A control circuit provides control signals to the memory arrays such that data is input and/or output to and from the memory device in multiples of nine bits. The data bits are input or output simultaneously without the need for multiplexing circuitry. This results in reduced power consumption and increased memory processing speed.Type: ApplicationFiled: June 23, 2003Publication date: January 29, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Hyang Ja Yang, Yong Hwan Noh, Yun Jin Cho, Chul Sung Park