Abstract: An operating method of a memory which can achieve high data reliability and a memory implementing the operating method are disclosed. In the event of errors in data stored in cells, the data is corrected using parity during a read operation. However, since the data with errors is stored in the cells, the data is corrected while the read operation is activated. This process ensures the reliability of the data.

Abstract: A method for restoring data and a non-volatile memory performing the restore operation are disclosed. If a restore command is applied, an internal read command is generated to sequentially designate the addresses. A read operation is performed on the designated address, and the number of error bits in a code word is compared with a reference number of error bits. Depending on the result of the comparison, an update or restore operation on a corrected code word for the designated address is selectively performed.

Abstract: A system for providing a reference voltage includes a tester adapted to provide a predetermined current, a first ground pad connected to a ground voltage of the tester, a second ground pad connected between the tester and the first ground pad, the second ground pad being connected to the tester through first and second resistors, a reference voltage pad connected to a node between the first and second resistors, the reference voltage pad adapted to provide a test reference voltage, and a multiplexer connected to the reference voltage pad, the multiplexer configured to output the test reference voltage as a reference voltage during substantial voltage variation.

Abstract: Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

Abstract: A transmission delay measuring circuit may include a first transmission path, a second transmission path, an inversion circuit, a first multiplexer, and an output terminal. The second transmission path may have the same structure as the structure of the first transmission path and may receive the output of the first transmission path. The inversion circuit may invert the output of the second transmission path. The first multiplexer may output one of the external input signal and an inverted output of the second transmission path to the first transmission path in response to a test mode enable signal. The output terminal may output, as a measuring signal, a signal in an arbitrary node of a closed loop formed of the first transmission path, the second transmission path, the inversion circuit, and the first multiplexer. The transmission delay measuring apparatus may more accurately measure the transmission delay of a transmission path in a semiconductor device in a die-to-die wafer state or a package state.

Abstract: Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

Abstract: Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

Abstract: A serial power capacitor device is provided which includes a noise suppressing circuit which includes a plurality of capacitive elements for suppressing a power noise, and a stabilizing circuit which stabilizes an operation of the noise suppressing circuit by compensating for variations in leakage current of the capacitive elements. The plurality of capacitive elements may, for example, be a plurality of power capacitors connected in series between a power source voltage and a ground voltage, and the stabilizing circuit may, for example, include a plurality of resistors connected in series between the power source voltage and the ground voltage. The resistors may, for example, be connected in parallel to the respective power capacitors, and a resistive value of each of the resistors may, for example, be less than an intrinsic resistive value of the power capacitors, respectively. The capacitive elements may, for example, be formed by DRAM cells or by metal oxide semiconductor (MOS) transistors.

Abstract: A system for providing a reference voltage includes a tester adapted to provide a predetermined current, a first ground pad connected to a ground voltage of the tester, a second ground pad connected between the tester and the first ground pad, the second ground pad being connected to the tester through first and second resistors, a reference voltage pad connected to a node between the first and second resistors, the reference voltage pad adapted to provide a test reference voltage, and a multiplexer connected to the reference voltage pad, the multiplexer configured to output the test reference voltage as a reference voltage during substantial voltage variation.

Abstract: A transmission delay measuring circuit may include a first transmission path, a second transmission path, an inversion circuit, a first multiplexer, and an output terminal. The second transmission path may have the same structure as the structure of the first transmission path and may receive the output of the first transmission path. The inversion circuit may invert the output of the second transmission path. The first multiplexer may output one of the external input signal and an inverted output of the second transmission path to the first transmission path in response to a test mode enable signal. The output terminal may output, as a measuring signal, a signal in an arbitrary node of a closed loop formed of the first transmission path, the second transmission path, the inversion circuit, and the first multiplexer. The transmission delay measuring apparatus may more accurately measure the transmission delay of a transmission path in a semiconductor device in a die-to-die wafer state or a package state.

Abstract: The invention is directed to data input/output organization system and method in a semiconductor memory device. The memory device has a plurality of memory arrays, in one embodiment, an odd number of memory arrays. The arrays are divided into blocks, and the blocks are divided into segments. A control circuit provides control signals to the memory arrays such that data is input and/or output to and from the memory device in multiples of nine bits. The data bits are input or output simultaneously without the need for multiplexing circuitry. This results in reduced power consumption and increased memory processing speed.

Abstract: Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.

Abstract: A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.

Abstract: An integrated circuit device includes a pin for receiving a DC voltage component signal. The device includes a signal source for applying an AC signal to the pin, a buffer for converting the AC signal into a digital signal, and a digital detector for detecting a frequency of the digital signal and outputting a predetermined detection signal. The predetermined detection signal is activated when the frequency of the digital signal is greater than or equal to a predetermined frequency. The predetermined detection signal is used as a signal for setting predetermined functional modes. The device further includes registers or a differential amplifier and a decoder for generating a plurality of functional mode signals.

Abstract: The invention is directed to data input/output organization system and method in a semiconductor memory device. The memory device has a plurality of memory arrays, in one embodiment, an odd number of memory arrays. The arrays are divided into blocks, and the blocks are divided into segments. A control circuit provides control signals to the memory arrays such that data is input and/or output to and from the memory device in multiples of nine bits. The data bits are input or output simultaneously without the need for multiplexing circuitry. This results in reduced power consumption and increased memory processing speed.

Abstract: The invention is directed to data input/output organization system and method in a semiconductor memory device. The memory device has a plurality of memory arrays, in one embodiment, an odd number of memory arrays. The arrays are divided into blocks, and the blocks are divided into segments. A control circuit provides control signals to the memory arrays such that data is input and/or output to and from the memory device in multiples of nine bits. The data bits are input or output simultaneously without the need for multiplexing circuitry. This results in reduced power consumption and increased memory processing speed.

Abstract: Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.

Abstract: Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.

Abstract: An integrated circuit device comprises a pin for receiving a DC voltage component signal. The device comprises a signal source for applying an AC signal to the pin, a buffer for converting the AC signal into a digital signal, and a digital detector for detecting a frequency of the digital signal and outputting a predetermined detection signal. The predetermined detection signal is activated when the frequency of the digital signal is greater than or equal to a predetermined frequency. The predetermined detection signal is used as a signal for setting predetermined functional modes. The device further comprises registers or a differential amplifier and a decoder for generating a plurality of functional mode signals.

Abstract: A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.