Abstract: A capacitor component includes a body having a first surface and a second surface opposing each other and including a multilayer structure in which a plurality of dielectric layers are stacked and first and second internal electrodes are alternately disposed with respective dielectric layers interposed therebetween and exposed to the first surface and the second surface, respectively, first and second metal layers covering the first surface and the second surface and connected to the first and second internal electrodes, respectively, first and second ceramic layers covering the first and second metal layers, and first and second external electrodes covering the first and second ceramic layers and connected to the first and second metal layers to be electrically connected to the first and second internal electrodes, respectively.

Abstract: A method of fabricating a three-dimensional semiconductor device comprises stacking first hardmask layers and second hardmask layers on a lower layer including a pattern region and a buffer region adjacent to the pattern region, the second hardmask layers and the first hardmask layers for forming a first hardmask pattern and a second hardmask pattern, patterning the second hardmask layer to form the second hardmask pattern including a plurality of first mask holes on the pattern region and at least one recess on the buffer region, the plurality of first mask holes exposing the first hardmask layer, and etching the first hardmask layer using the second hardmask pattern as an etch mask to form the first hardmask pattern including a plurality of etch mask holes on the pattern region and at least one buffer mask hole on the buffer region, the plurality of etch mask holes exposing a top surface of the lower layer, the at least one buffer mask hole having a bottom surface spaced apart from the top surface of the lo

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

Abstract: A method of fabricating a three-dimensional semiconductor device comprises stacking first hardmask layers and second hardmask layers on a lower layer including a pattern region and a buffer region adjacent to the pattern region, the second hardmask layers and the first hardmask layers for forming a first hardmask pattern and a second hardmask pattern, patterning the second hardmask layer to form the second hardmask pattern including a plurality of first mask holes on the pattern region and at least one recess on the buffer region, the plurality of first mask holes exposing the first hardmask layer, and etching the first hardmask layer using the second hardmask pattern as an etch mask to form the first hardmask pattern including a plurality of etch mask holes on the pattern region and at least one buffer mask hole on the buffer region, the plurality of etch mask holes exposing a top surface of the lower layer, the at least one buffer mask hole having a bottom surface spaced apart from the top surface of the lo

Abstract: A method of manufacturing a semiconductor device includes alternately stacking mold insulating layers and sacrificial layers on a substrate; forming channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing recessed regions to be formed in the substrate; cleaning a surface of the recessed regions in such a manner that processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the recessed regions in a lower portion of the channel holes are alternately repeated one or more times, in-situ; and forming epitaxial layers on the recessed regions of the substrate.

Abstract: A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure penetrates the stack in the cell region. The stack includes electrode patterns and insulating patterns which are alternatingly and repeatedly stacked on the substrate. Each of the electrode patterns may extend in a first direction and include a pad portion. The pad portion is positioned in the connection region. The pad portion includes a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion. The first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

Abstract: A method of manufacturing a semiconductor device includes alternately stacking mold insulating layers and sacrificial layers on a substrate; forming channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing recessed regions to be formed in the substrate; cleaning a surface of the recessed regions in such a manner that processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the recessed regions in a lower portion of the channel holes are alternately repeated one or more times, in-situ; and forming epitaxial layers on the recessed regions of the substrate.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

Abstract: A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure penetrates the stack in the cell region. The stack includes electrode patterns and insulating patterns which are alternatingly and repeatedly stacked on the substrate. Each of the electrode patterns may extend in a first direction and include a pad portion. The pad portion is positioned in the connection region. The pad portion includes a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion. The first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall.

Abstract: Disclosed are a semiconductor memory device and a method of checking an operation state thereof. The semiconductor memory device includes: a micro configured to output a data generating code according to a state checking operation command; and a step code generating unit configured to generate a step code for an operation currently performed by a storage device according to the data generating code, and output ROM data including the step code, in which the micro generates a state code for the operation currently performed by the storage device and an operation code for a segmentalized step of the operation according to the ROM data.

Abstract: A metal panel, a manufacturing method thereof and a cooking device using the metal panel capable of improving an external appearance of edges, enhancing efficiency of a manufacturing process and reducing the manufacturing cost. The manufacturing method of a metal panel includes cutting a metal plate to form a cutaway portion at a specified area of a border, bending the border on opposite sides of the cutaway portion, and coupling a bracket to a cutaway groove formed at the border by the bending.

Abstract: According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

Abstract: A machine room cooling structure of an oven which relatively enlarges the inner volume of a cooking room by lowering the height of the machine room is provided. The machine room cooling structure includes a fan forcibly blowing air of the machine room, a motor driving the fan, an exhaust duct guiding air of the machine room to an area in front of the oven, and a support bracket to install the motor at a suction hole of the exhaust duct, the support bracket includes a base unit, a motor combining unit on which a core of the motor is placed, and bridge parts connecting the base unit and the motor combining unit, and the motor combining unit is formed such that the height of the lower end of the core is equal to or lower than the height of the upper end of the exhaust duct.

Abstract: Provided is a heating cooker which allows a door on a cooking chamber to be opened without direct handling of the door by a user. The heating cooker includes a body having a cooking chamber defined therein, a door hingably mounted to the body to open and close the cooking chamber, a door holder positioned in the body to hold the door and keep the cooking chamber closed by the door, and a hinge part connected between the door and the body to guide rotation of the door such that when the door is released from the door holder, the door is automatically opened.

Abstract: According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

Abstract: A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.

Abstract: Methods of forming patterns in semiconductor devices are provided including forming first patterns spaced apart from one another on an object structure. A first sacrificial layer is formed conformally on the first patterns and the object structure. A second pattern is formed on a sidewall of the first sacrificial layer, the second pattern having a height smaller than that of the first pattern from an upper surface of the object structure. The first patterns are selectively removed to form an opening that exposes the object structure. A third pattern is formed on a sidewall of the opening.