Abstract: A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The semiconductor package may include one or more reconfigurable package units each including a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch on a second active surface; a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch; a molding layer surrounding side surfaces of the second semiconductor chip and the semiconductor chip connector; and redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer.

Abstract: A display device includes a display panel and a touch sensor which is disposed on the display panel. The display panel includes a display unit including a pixel, a driving circuit unit disposed outside the display unit, and a first static electricity blocking layer disposed on the driving circuit unit. The touch sensor includes sensing electrodes disposed on the display unit and a second static electricity blocking layer disposed overlapping the first static electricity blocking layer outside of the sensing electrodes.

Abstract: Disclosed is a contents providing method of a computing apparatus. The contents providing method includes storing highlighted contents in a storage unit; searching the highlighted contents based on a search condition; reading the highlighted contents from the storage unit according to a search result; and providing the read highlighted contents to a user via a display unit.

Abstract: A motor fixing structure and a motor assembly capable of reducing vibration of a motor and also maintaining a compact configuration. The motor assembly includes a motor, a fixing member disposed to be spaced from the motor by a predetermined spacing distance, and a vibration absorbing member to prevent vibration of the motor from being transferred to the fixing member, wherein the vibration absorbing member is formed to be longer by a predetermined specified length than the predetermined spacing distance between the motor and the fixing member and is disposed outside of a periphery of the motor.

Abstract: Disclosed are a wheel assembly and wheeled shoes having the same. According to an embodiment of the invention, a wheel assembly, being installed in a way to allow wheel(s) to be retracted into or pulled out of an inner space, includes: a base block fixed in the inner space; a wheel support, to which the wheel(s) is (are) rotatably coupled and which is pivotably mounted on the base block about a first axis, thus pivoting between a first position where the wheel(s) is (are) retracted into the inner space and a second position where the wheel(s) is (are) pulled out of the inner space; and a positioner, which enables the wheel support to pivot between the first position and the second position and fixes the position of the wheel support to prevent the wheel support from pivoting on the base block when the wheel support is located in the first position or in the second position.

Abstract: A high speed interface type device can reduce power consumption and a circuit area, and transmit/receive a 4 bit data in one clock period. The high speed interface type device includes a DRAM unit for generating first clock and clock bar signals which do not have a phase difference from a main clock signal, and second clock and clock bar signals having 90° phase difference from the first clock and clock bar signals in a write operation, storing an inputted 4 bit data in one period of the main clock signal according to the first clock to second clock bar signals, synchronizing the stored data with data strobe signals according to the first clock to second clock bar signals in a read operation, and outputting a 4 bit data in one period of the main clock signal, and a controller for transmitting a command, address signal and data signal synchronized with the main clock signal to the DRAM unit in the write operation, and receiving data signals from the DRAM unit in the read operation.

Abstract: The present invention discloses a high speed interface type semiconductor memory device which can transmit data of a plurality of DRAMs of a module to a controller by using only one data strobe clock signal. The high speed interface type semiconductor memory device includes a DRAM module unit for generating a strobe clock signal for synchronizing a data signal in a read operation in a DRAM farthest from a controller among a plurality of DRAMs, providing the strobe clock signal to the other DRAMs, and transmitting data to the controller in the read operation, and a controller for transmitting a clock signal and data signals synchronized with the clock signal to the plurality of DRAMs, and receiving data signals from the DRAMs.

Abstract: A synchronous semiconductor device having a delay locked loop capable of adjusting phase offset between an external clock signal and an internal clock signal after a packaging process is completed is disclosed. The disclosed synchronous semiconductor device may include a replica delay for replicating delay time of an internal circuit and a delay controller for controlling the replicated delay time.

Abstract: A synchronous semiconductor device having a delay locked loop capable of adjusting phase offset between an external clock signal and an internal clock signal after a packaging process is completed is disclosed. The disclosed synchronous semiconductor device may include a replica delay for replicating delay time of an internal circuit and a delay controller for controlling the replicated delay time.

Abstract: The present invention discloses a high speed interface type semiconductor memory device which can transmit data of a plurality of DRAMs of a module to a controller by using only one data strobe clock signal. The high speed interface type semiconductor memory device includes a DRAM module unit for generating a strobe clock signal for synchronizing a data signal in a read operation in a DRAM farthest from a controller among a plurality of DRAMs, providing the strobe clock signal to the other DRAMs, and transmitting data to the controller in the read operation, and a controller for transmitting a clock signal and data signals synchronized with the clock signal to the plurality of DRAMs, and receiving data signals from the DRAMs.

Abstract: A high speed interface type device can reduce power consumption and a circuit area, and transmit/receive a 4 bit data in one clock period. The high speed interface type device includes a DRAM unit for generating first clock and clock bar signals which do not have a phase difference from a main clock signal, and second clock and clock bar signals having 90° phase difference from the first clock and clock bar signals in a write operation, storing an inputted 4 bit data in one period of the main clock signal according to the first clock to second clock bar signals, synchronizing the stored data with data strobe signals according to the first clock to second clock bar signals in a read operation, and outputting a 4 bit data in one period of the main clock signal, and a controller for transmitting a command, address signal and data signal synchronized with the main clock signal to the DRAM unit in the write operation, and receiving data signals from the DRAM unit in the read operation.

Abstract: The present invention relates to a command latency circuit for a programmable SynchLink Dynamic Random Access Memory (SLDRAM) which is an ultrahigh speed memory device. The command latency circuit for the SLDRAM includes: a command decoder unit for decoding and outputting an input of a command address; an internal clock generating unit for outputting an internal clock according to an input of a master clock while a latency is operated; a register decoder unit for receiving and decoding a register data; a burst control unit for receiving the output signal from the command decoder unit and the internal clock, and outputting a command pulse; a shift register unit for shift-outputting the output signal from the burst control unit according to an input of the internal clock; and an output unit for receiving the output signals from the shift register unit and the register decoder unit, and outputting a command signal having a wanted delay.

Abstract: A temperature controller for bedding which can always provide a comfortable sleeping environment by maintaining bedding at a temperature suitable for the human body during sleeping by supplying cold or warm heat transfer medium to the inside of bedding, such as a floor mat or a bed mattress according to a preset temperature and a preset time.