Patents by Inventor Yong Jin

Yong Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240381675
    Abstract: A method includes obtaining a set of tandem solar cell devices, and forming, on each tandem solar cell device of the set of tandem solar cell devices using a deposition process, a discrete encapsulation layer along an upper surface and side surfaces of the tandem solar cell device.
    Type: Application
    Filed: April 29, 2024
    Publication date: November 14, 2024
    Inventors: Yongkee Chae, Yong Jin Kim, Cheng-Pei Ouyang, Su-Ho Cho
  • Publication number: 20240379357
    Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wei-Chao CHIU, Yong-Jin LIOU, Yu-Wen CHEN, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Publication number: 20240381753
    Abstract: A method includes obtaining a base structure of a tandem solar cell device and forming a transparent conductive oxide (TCO) layer on the base structure using a low damage sputter deposition (LDSD) process. The LDSD process includes a rotary facing sputter deposition process.
    Type: Application
    Filed: April 29, 2024
    Publication date: November 14, 2024
    Inventors: Yongkee Chae, Xun Li, Jun-Nan Liu, Shinobu Abe, Cheng-Pei Ouyang, Su-Ho Cho, Yong Jin Kim, Thomas Werner Zilbauer
  • Patent number: 12133550
    Abstract: A molding apparatus, a cigarette filter rod and a preparation method thereof are disclosed. The molding apparatus comprises a single-screw extrusion system and a cooling setting system. The single-screw extrusion system comprises a feeder and an extruder. The feeder is arranged on the extruder. The extruder comprises a cylinder. A heater is arranged outside the cylinder. A screw is arranged inside the cylinder, and a mouth mold is arranged at one end of the cylinder. The cooling setting system comprises a round tube and a cooler. The cooler (6) is arranged outside the round tube. One end of the round tube is butted with the mouth mold of the extruder; and multiple groups of grooves are formed on threads of the head of the screw.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 5, 2024
    Assignee: CHINA TOBACCO HUNAN INDUSTRIAL CO., LTD.
    Inventors: Qian Chen, Yong Jin, Ke Li, Shitai Wang, Chao Tan, Saibo Yu, Haifeng Tan, Hongmei Fan, Qi Liu
  • Publication number: 20240355675
    Abstract: Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule, such as a boron-containing compound, to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface.
    Type: Application
    Filed: April 9, 2024
    Publication date: October 24, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Muthukumar Kaliappan, Yong Jin Kim, Carmen Leal Cervantes, Bhaskar Jyoti Bhuyan, Xiangjin Xie, Michael Haverty, Kevin Kashefi, Mark Saly, Aaron Dangerfield, Jesus Candelario Mendoza-Gutierrez
  • Publication number: 20240339358
    Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM has a general formula I to XIX, wherein R, R?, R1, R2, R3, R4, and R5 are independently selected from hydrogen (H), alkyl, alkene, alkyne, and aryl, n is from 1 to 20, m is from 1 to 20, x is from 1 to 2, and y is from 1 to 2. A barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.
    Type: Application
    Filed: April 7, 2023
    Publication date: October 10, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Jesus Candelario Mendoza-Gutierrez, Aaron Dangerfield, Bhaskar Jyoti Bhuyan, Mark Saly, Yang Zhou, Yong Jin Kim, Carmen Leal Cervantes, Ge Qu, Zhiyuan Wu, Feng Chen, Kevin Kashefi
  • Publication number: 20240340679
    Abstract: A method of identifying an artificial intelligence (AI)/machine learning (ML) functionality and model supported for mobile communication operated in a mobile communication system including a base station and one or more user equipments (UEs), the method comprising: delivering, from the base station, dataset identification information regarding at least one dataset to the UE; and reporting, by the UE, valid AI/ML-related UE capability for the at least one dataset corresponding to the dataset identification information to the base station.
    Type: Application
    Filed: April 5, 2024
    Publication date: October 10, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Han Jun PARK, Yong Jin KWON, An Seok LEE, Heesoo LEE, Yun Joo KIM, Hyun Seo PARK, Jung Bo SON, Yu Ro LEE
  • Publication number: 20240339135
    Abstract: A semiconductor device may include a first contact plug, a word line electrically connected to the first contact plug and extending in a first direction, a second contact plug, a bit line extending in a second direction that intersects the first direction, and a memory cell disposed between the word line and the bit line and including a variable resistance layer. The bit line may include a first protruding part that protrudes into the memory cell, a second protruding part that is connected to the second contact plug, and a connection part that connects the first protruding part and the second protruding part and that extends in the second direction.
    Type: Application
    Filed: August 4, 2023
    Publication date: October 10, 2024
    Inventors: Yong Jin JEONG, Sang Gu YEO
  • Patent number: 12110290
    Abstract: Compounds having formula (I), and enantiomers, and diastereomers, stereoisomers, pharmaceutically-acceptable salts thereof, are useful as kinase modulators, including RIPK1 modulation. All the variables are as defined herein.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: October 8, 2024
    Assignee: Bristol-Myers Squibb Company
    Inventors: Guanglin Luo, Jie Chen, Carolyn Diane Dzierba, David B. Frennesson, Junqing Guo, Amy C. Hart, Xirui Hu, Michael E. Mertzman, Matthew Reiser Patton, Jianliang Shi, Steven H. Spergel, Brian Lee Venables, Yong-Jin Wu, Zili Xiao, Michael G. Yang
  • Publication number: 20240334714
    Abstract: A manufacturing method may include forming an opening within a stack, forming a variable resistance layer within the opening and on the stack, forming a conductive layer on the variable resistance layer, forming a conductive pattern including a first part within the opening and a second part on the stack, by etching the conductive layer, forming a variable resistance pattern including a first part within the opening and a second part on the stack, by etching the variable resistance layer, and planarizing the conductive pattern and the variable resistance pattern until the stack is exposed.
    Type: Application
    Filed: August 31, 2023
    Publication date: October 3, 2024
    Inventors: Sang Gu YEO, Yong Jin JEONG
  • Publication number: 20240327746
    Abstract: Proposed is an aqueous suspension including water, a hexagonal boron nitride (hBN) particle, and a dispersant. A cutting fluid prepared by diluting the aqueous suspension with water is also proposed. The hexagonal boron nitride (hBN) particle is a hydrophilic particle that is wettable with water. The hexagonal boron nitride (hBN) particle has a particle size D50 of 30 to 250 nm and a particle size D90 of 1 um or less for a primary particle and a secondary particle through an application of ultrasound for 24 hours. The hexagonal boron nitride (hBN) particle is synthesized at a temperature of 1600° C. or lower. The hexagonal boron nitride (hBN) particle is mixed with water at a weight ratio of 10 or less, and the dispersant is mixed at a weight ratio of 10 or less.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Applicant: MICRO-COMPOSITE INC.
    Inventors: Don Chul CHOI, Yong Jin KIM
  • Publication number: 20240332075
    Abstract: Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a first self-assembled monolayer (SAM) on the bottom of the gap; forming a barrier layer on the dielectric layer; selectively depositing a second self-assembled monolayer (SAM) on the barrier layer and on the bottom of the gap; treating the microelectronic device with a plasma to remove a first portion of the second self-assembled monolayer (SAM); selectively depositing a metal liner on the barrier layer on the sidewall; removing a second portion of the second self-assembled monolayer (SAM); and performing a gap fill process on the metal liner.
    Type: Application
    Filed: March 22, 2024
    Publication date: October 3, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Jiajie Cen, Kevin Kashefi, Zhiyuan Wu, Yang Zhou, Yong Jin Kim, Carmen Leal Cervantes, Ge Qu, Zheng Ju
  • Patent number: 12103408
    Abstract: An energy-independent water electrolysis fuel cell water vehicle system is suggested. The energy-independent water electrolysis fuel cell water vehicle system suggested in the present invention comprises: a water electrolysis processing unit for performing a water electrolysis process by using supplied water while power is not being received from the outside; a gas control unit for adjusting the pressure of a hydrogen gas produced through the water electrolysis process, storing the hydrogen gas in a hydrogen storage by using a gas compression method, and then supplying the hydrogen gas; a fuel cell for generating electrical energy on the basis of the supplied hydrogen gas; and a power control unit for supplying the generated electrical energy as a driving power for the energy-independent water electrolysis fuel cell water vehicle system.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: October 1, 2024
    Assignee: KWATERCRAFT CO., LTD.
    Inventors: Yong Jin Kwon, Nam Ju Cho
  • Patent number: 12100592
    Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chao Chiu, Yong-Jin Liou, Yu-Wen Chen, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu
  • Patent number: 12097696
    Abstract: Provided are a fringe information measuring apparatus that measures information on a fringe region using a temperature sensor array and a substrate treating system including the same. The fringe information measuring apparatus comprises: a laser sensor configured to output a first laser light and a second laser light to intersect each other; a thermal sensor array configured to pass through a fringe region formed by the intersection of the first laser light and the second laser light; and a control module configured to measure a position of the fringe region based on information obtained when the thermal sensor array passes through the fringe region.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: September 24, 2024
    Assignee: SEMES CO., LTD.
    Inventors: Jae Duck Lee, Han Lim Kang, Won Yong Jin, Suk Won Jang
  • Publication number: 20240314612
    Abstract: A method of a terminal may comprise: receiving, from a serving cell, a first message including measurement report configuration information; in response to transmission of a measurement report message being triggered based on the first message, generating a measurement report message; and in response to a measurement report message transmission condition configured by the first message being satisfied, transmitting the measurement report message to the serving cell.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 19, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyun Seo PARK, Yong Jin KWON, Yun Joo KIM, Han Jun PARK, Jung Bo SON, An Seok LEE, Yu Ro LEE, Sung Cheol CHANG, Heesoo LEE
  • Publication number: 20240297073
    Abstract: Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 5, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Muthukumar Kaliappan, Bhaskar Jyoti Bhuyan, Yong Jin Kim, Carmen Leal Cervantes, Xiangjin Xie, Jesus Candelario Mendoza-Gutierrez, Aaron Dangerfield, Michael Haverty, Mark Saly, Kevin Kashefi
  • Patent number: 12075560
    Abstract: A printed circuit board includes a first electrically conductive reference plane configured to distribute a first reference voltage applied thereto across a surface area of the first reference plane, and a second electrically conductive reference plane extending parallel to the first reference plane, and configured to distribute a second reference voltage applied thereto across a surface area of the second reference plane. A first layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more first signal lines extending adjacent the first reference plane. The first layer is divided into: (i) a first region in which the one or more first signal lines are disposed, (ii) a second region containing an additional plane that is configured to receive a third voltage and has smaller surface area relative to the surface areas of the first and second reference planes, and (iii) a third region containing a dielectric layer.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: August 27, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hyun Seok, Yong-Jin Kim, Kyeongseon Park, Hwanwook Park
  • Patent number: D1050548
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: November 5, 2024
    Inventor: Yong Jin
  • Patent number: D1050549
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: November 5, 2024
    Inventor: Yong Jin