Patents by Inventor Yong Ju

Yong Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180219216
    Abstract: The present invention relates to a silicon-carbon-based composite negative electrode active material, and a negative electrode for a secondary battery and a lithium secondary battery including the same, and particularly to a silicon-carbon-based composite negative electrode active material, in which physical stability is improved by including a carbon-based core capable of intercalating and deintercalating lithium ions and at least one silicon particle included in the carbon-based core and disposed in the form of being distributed in an outer portion of the carbon-based core, and a negative electrode for a secondary battery and a lithium secondary battery in which life characteristics are improved by including the same.
    Type: Application
    Filed: April 20, 2017
    Publication date: August 2, 2018
    Applicant: LG Chem, Ltd.
    Inventors: Jung Hyun Choi, Yong Ju Lee, Eun Kyung Kim
  • Publication number: 20180219225
    Abstract: The present invention relates to a negative electrode active material and a secondary battery including the same, and specifically, provides a negative electrode active material particle including a core, which includes a carbon-based active material and an oxygen functional group, and a shell, which surrounds the core and includes a silicon-based active material.
    Type: Application
    Filed: October 17, 2016
    Publication date: August 2, 2018
    Applicant: LG CHEM, LTD.
    Inventors: Jung Hyun CHOI, Yong Ju LEE, Eun Kyung KIM, Hyun Chul KIM
  • Patent number: 10038451
    Abstract: An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 31, 2018
    Assignees: SK HYNIX INC., POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Jae Yoon Sim, Min Seob Lee, In Hwa Jung, Yong Ju Kim
  • Patent number: 10038060
    Abstract: An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (Vg) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: July 31, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Yong Ju Lee, Yang Du
  • Publication number: 20180202942
    Abstract: A method for measuring a semiconductor device is provided. A method for measuring a semiconductor device includes defining an interest area and an acceptable area in a chip area on a wafer; performing a first measurement of the chip area with a spectral imaging device to acquire spectrum data of the chip area; assuming the distribution of the spectrum data of a first pixel in the acceptable area is a normal distribution; calculating a distance from a central point on the normal distribution to second pixels in the interest area; selecting a position of a second pixel having a distance from the central point on the normal distribution greater than a predetermined range, among the second pixels, as a candidate position; and performing a second measurement of the candidate position.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 19, 2018
    Inventors: Hyo Hyeong KANG, Kang Woong KO, Sung Yoon RYU, Gil Woo SONG, Jae Hyung AHN, Chul Hyung YOO, Kyoung Hwan LEE, Sung Ho JANG, Yong Ju JEON, Hyoung Jo JEON
  • Publication number: 20180202672
    Abstract: A floating-type humidifier container according to an exemplary embodiment of the present invention includes: a lower body having a space portion which is opened at an upper side thereof and accommodates water therein so that a floating-type humidifier floats on the water; and an upper body having an opening portion provided in an upper portion of the upper body so that one end of the floating-type humidifier is penetratively inserted into the opening portion, in which the upper body includes an inclined portion which is formed to be inclined downward toward a center of the space portion so that humidification particles discharged from the floating-type humidifier are introduced into the space portion through the opening portion.
    Type: Application
    Filed: July 11, 2016
    Publication date: July 19, 2018
    Inventors: Dong Jin SEO, Yong Ju OH, Min Seok KIM
  • Publication number: 20180197320
    Abstract: Disclosed is an apparatus and method for processing information of multiple cameras.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 12, 2018
    Applicant: Electronics and Telecommunications Research Instit ute
    Inventors: Seong Yong LIM, Yong Ju CHO, Jeong Il SEO, Joo Myoung SEOK
  • Patent number: 10019197
    Abstract: A semiconductor system may include: a command queue suitable for storing a plurality of requests provided from a host according to rank and bank information of the requests; one or more determination units suitable for determining requests having a same row address in response to row address information of the requests stored in the command queue; an arbitration unit suitable for scheduling the plurality of requests according to internal priorities of the requests; a monitoring unit suitable for providing the rank information and row hit information of the plurality of requests outputted according to the scheduling result of the arbitration unit, to the arbitration unit; a command generation unit suitable for generating a plurality of commands corresponding to and in response to the plurality of requests outputted according to the scheduling result of the arbitration unit; and a semiconductor memory device suitable for performing an internal operation in response to the command, wherein the arbitration unit r
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: July 10, 2018
    Assignee: SK Hynix Inc.
    Inventors: Kyung-Min Lee, Yong-Ju Kim
  • Publication number: 20180183447
    Abstract: An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.
    Type: Application
    Filed: October 27, 2017
    Publication date: June 28, 2018
    Inventors: Jae Yoon SIM, Min Seob LEE, In Hwa JUNG, Yong Ju KIM
  • Patent number: 10009545
    Abstract: An image processing apparatus and method are provided. The apparatus includes an image obtainer configured to obtain a captured image; a quick view image generator configured to generate a quick view image showing a region of the captured image based on a user profile determined according to a type of the captured image; and a display unit configured to display the generated quick view image according to a preset method.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jong-hyon Park, Yong-ju Lee, Jun-hyuk Ko, Kyoung-joon Park
  • Publication number: 20180176126
    Abstract: A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 21, 2018
    Inventors: Hong June PARK, Soo Min LEE, Yong Ju KIM, Hae Kang JUNG
  • Publication number: 20180163266
    Abstract: Methods and apparatuses for sensing nucleotides are disclosed. A related nucleotide sensing device may include an insulator having an electrode well and a separation layer attached to the insulator, the separation layer including a film and a shell layer. The film may have a hole, the hole having a first diameter. The shell layer may be disposed on a surface of the film, and at least a portion of the shell layer may be disposed within the hole. The separation layer may be formed of inorganic material and may comprise a nanopore. The nanopore may permit fluid communication with the electrode well across the separation layer. The nanopore may be disposed within the hole and may have a second diameter smaller than the first diameter.
    Type: Application
    Filed: December 8, 2016
    Publication date: June 14, 2018
    Inventors: Tallis Young CHANG, Yaoling PAN, Yong Ju LEE
  • Publication number: 20180165187
    Abstract: a semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.
    Type: Application
    Filed: August 22, 2017
    Publication date: June 14, 2018
    Inventors: Yong-Ju KIM, Dong-Gun KIM, Do-Sun HONG
  • Publication number: 20180166685
    Abstract: The present invention relates to a porous silicon-silicon oxide-carbon composite comprising a silicon oxide-carbon structure and silicon particles, wherein the silicon oxide-carbon structure comprises a plurality of micropores, and the silicon particles are uniformly distributed in the silicon oxide-carbon structure. The porous silicon-silicon oxide-carbon composite of the present invention shows decreased volume expansion due to the intercalation of lithium ions and improved electric conductivity, and has a porous structure. Accordingly, an electrolyte easily penetrates into the porous structure, and output properties may be improved. When the composite is included in a negative electrode active material, the performance of a lithium secondary battery may be further improved.
    Type: Application
    Filed: March 30, 2016
    Publication date: June 14, 2018
    Applicants: LG Chem, Ltd., Korea Advanced Institute Of Science And Technology
    Inventors: Seung Youn Choi, Jang Wook Choi, Eun Kyung Kim, Yong Ju Lee, Hye Jin Kim
  • Patent number: D821555
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 26, 2018
    Assignee: MIRO CO. LTD.
    Inventors: Dong Jin Seo, Yong Ju Oh, Min Seok Kim, Jeong Won Lee
  • Patent number: D822813
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: July 10, 2018
    Assignee: MIRO CO. LTD.
    Inventors: Dong Jin Seo, Yong Ju Oh, Min Seok Kim, Jeong Won Lee
  • Patent number: D822814
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 10, 2018
    Assignee: MIRO CO. LTD.
    Inventors: Dong Jin Seo, Yong Ju Oh, Min Seok Kim, Jeong Won Lee
  • Patent number: D822815
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 10, 2018
    Assignee: MIRO CO. LTD.
    Inventors: Dong Jin Seo, Yong Ju Oh, Min Seok Kim, Jeong Won Lee
  • Patent number: D822816
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: July 10, 2018
    Assignee: MIRO CO. LTD.
    Inventors: Dong Jin Seo, Yong Ju Oh, Min Seok Kim, Jeong Won Lee
  • Patent number: D823450
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 17, 2018
    Assignee: MIRO CO., LTD.
    Inventors: Dong Jin Seo, Yong Ju Oh, Min Seok Kim, Jeong Won Lee