Patents by Inventor Yong Ju

Yong Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Porous silicon-based anode active material, method of preparing the same, and lithium secondary battery including the anode active material
    Patent number: 9843034
    Abstract: Provided are a porous silicon-based anode active material including crystalline silicon (Si) particles, and a plurality of pores on surfaces, or the surfaces and inside of the crystalline silicon particles, wherein at least one plane of crystal planes of at least a portion of the plurality of pores includes a (100) plane, and a method of preparing the porous silicon-based anode active material. Since a porous silicon-based anode active material of the present invention may allow volume expansion, which is occurred during charge and discharge of a lithium secondary battery, to be concentrated on pores instead of the outside of the anode active material, the porous silicon-based anode active material may improve life characteristics of the lithium secondary battery by efficiently controlling the volume expansion.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 12, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Yong Ju Lee, Mi Rim Lee, Jung Woo Yoo, Je Young Kim
  • Semiconductor system including replacement storage unit
    Patent number: 9842035
    Abstract: A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: December 12, 2017
    Assignee: SK Hynix Inc.
    Inventors: Kyung-Min Lee, Young-Ook Song, Ki-Joong Kim, Yong-Ju Kim, Jung-Hyun Kwon, Sang-Gu Jo
  • MEMORY CONTROLLERS, MEMORY SYSTEMS, AND METHODS RELATING TO WEAR-LEVELING
    Publication number: 20170344278
    Abstract: A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.
    Type: Application
    Filed: April 21, 2017
    Publication date: November 30, 2017
    Applicant: SK hynix Inc.
    Inventors: Do-Sun HONG, Jung Hyun KWON, Donggun KIM, Yong Ju KIM, Sungeun LEE, Jae Sun LEE, Sang Gu JO, JINGZHE XU
  • Porous electrode active material and secondary battery including the same
    Patent number: 9831500
    Abstract: Provided are an electrode active material having a plurality of pores and a secondary battery including the same, and more particularly, a porous electrode active material including silicon-based oxide expressed by SiOx (0.5?x?1.2) and having a Brunauer, Emmett, and Teller (BET) specific surface area ranging from 2 m2/g to 100 m2/g, and a secondary battery including a cathode including a cathode active material, a separator, an anode including an anode active material, and an electrolyte, in which the anode active material includes a porous electrode active material including silicon-based oxide expressed by SiOx (0.5?x?1.2) and having a BET specific surface area ranging from 2 m2/g to 100 m2/g.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: November 28, 2017
    Assignees: LG Chem, Ltd., UNIST (Ulsan National Institute of Science and Technology)
    Inventors: Yong Ju Lee, Soo Jin Park, Dong Sub Jung, Hye Ran Jung, Jung In Lee, Je Young Kim, Jae Phil Cho
  • GRAPHENE NMOS TRANSISTOR USING NITROGEN DIOXIDE CHEMICAL ADSORPTION
    Publication number: 20170338311
    Abstract: An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (Vg) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 23, 2017
    Inventors: Yong Ju LEE, Yang DU
  • MEMORY MODULE, SYSTEM INCLUDING THE SAME
    Publication number: 20170329389
    Abstract: In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 16, 2017
    Inventors: Yong Ju KIM, Jung Hyun KWON, Donggun KIM, Sungeun LEE, Jae Sun LEE, Sang Gu JO, Jingzhe XU, Do Sun HONG
  • ENHANCED DYNAMIC MEMORY MANAGEMENT WITH INTELLIGENT CURRENT/POWER CONSUMPTION MINIMIZATION
    Publication number: 20170329385
    Abstract: A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices. Additionally, a current/power consumption may be obtained for each memory bank within each of the plurality of volatile memory devices. Data is then copied from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower current/power consumption than the first set of memory banks. The first set of volatile memory devices and/or first set of memory banks are then placed into a power-down state.
    Type: Application
    Filed: August 2, 2017
    Publication date: November 16, 2017
    Inventors: Hee Jun Park, Richard Gerard Hofmann, Yong Ju Lee
  • MEMORY SYSTEM AND OPERATION METHOD OF THE SAME
    Publication number: 20170329726
    Abstract: A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.
    Type: Application
    Filed: September 6, 2016
    Publication date: November 16, 2017
    Inventors: Sung-Eun LEE, Jung-Hyun KWON, Jing-Zhe XU, Yong-Ju KIM
  • METHOD AND APPARATUS FOR INCREASING A LIFESPAN OF NANOPORE-BASED DNA SENSING DEVICES
    Publication number: 20170321342
    Abstract: Techniques for increasing the lifespan of a nanopore DNA sensing device are disclosed. A related method may include forming a first electrode, forming a second electrode, disposing the first electrode and second electrode within an insulator, and disposing a lipid bilayer having a nanopore between the first electrode and second electrode. The forming of the second electrode may comprise forming a silver (Ag) layer, pressing a mold into the Ag layer to form a pattern in the Ag layer, removing the mold from the Ag layer, and exposing the Ag layer to an electrolyte.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 9, 2017
    Inventors: Yong Ju LEE, Vladimir APARIN
  • Negative electrode active material for lithium secondary battery and lithium secondary battery comprising the same
    Patent number: 9812705
    Abstract: Provided is a negative electrode active material comprising (a) a core including one or more non-carbon-based materials selected from the group consisting of silicon, nickel, germanium, and titanium, and (b) an organic polymer coating layer formed of a polymer compound having a content of a fluorine component of 50 wt % or more on a surface of the core.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: November 7, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Yoon Ah Kang, Je Young Kim, Yong Ju Lee, Jin Hyong Lim, Hoon Jeong, Ki Hwan Kim
  • Composite including conductive material and binder on surface of (semi) metal oxide and method of preparing anode slurry including the same
    Patent number: 9806335
    Abstract: Provided are a composite and a method of preparing an anode slurry including the same. More particularly, the present invention provides a composite including a (semi) metal oxide, a conductive material on a surface of the (semi) metal oxide, and a binder, and a method of preparing an anode slurry including preparing a composite by dispersing a conductive material in an aqueous binder and then mixing with a (semi) metal oxide, and mixing the composite with a carbon material and a non-aqueous binder.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: October 31, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Yoon Ah Kang, Yong Ju Lee, Rae Hwan Jo, Je Young Kim
  • NEGATIVE ELECTRODE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY, METHOD OF PREPARING THE SAME, AND LITHIUM SECONDARY BATTERY INCLUDING THE MATERIAL
    Publication number: 20170309902
    Abstract: Provided are a negative electrode active material for a lithium secondary battery and a method of preparing the same, wherein since the negative electrode active material includes porous polycrystalline silicon and the porous polycrystalline silicon includes pores disposed at grain boundaries, the negative electrode active material may exhibit a buffering action by internally absorbing changes in volume of the active material during charge and discharge. As a result, lifetime characteristics of a negative electrode and a battery may be improved.
    Type: Application
    Filed: October 1, 2015
    Publication date: October 26, 2017
    Applicant: LG Chem, Ltd.
    Inventors: Rae Hwan Jo, Ju Ho Chung, Eun Kyung Kim, Yong Ju Lee, Seung Youn Choi, Hyun Chul Kim, Jung Hyun Choi
  • LITHIUM-SULFUR BATTERY
    Publication number: 20170309949
    Abstract: The present invention provides: i) a lithium-sulfur battery in which solid sulfur is introduced into an electrolytic region between a positive electrode and a negative electrode; ii) a lithium-sulfur battery comprising a middle layer containing elemental sulfur (S8) or lithium sulfide (Li2S) in an electrolytic region between a positive electrode and a negative electrode; and iii) a lithium-sulfur battery having a separator supporting sulfur particles or lithium sulfide particles between a positive electrode and a negative electrode.
    Type: Application
    Filed: November 12, 2015
    Publication date: October 26, 2017
    Applicant: J-INNOTECH CO., LTD
    Inventors: Yong Ju Jung, Jeong Yoon Koh
  • SILICON-BASED NEGATIVE ELECTRODE ACTIVE MATERIAL AND METHOD FOR PREPARING THE SAME
    Publication number: 20170309893
    Abstract: A negative electrode active material of the present invention includes a core containing silicon-based nanoparticles and polymer carbides distributed on the nanoparticles, wherein the core has a size of 30-300 nm, and such a negative electrode active material is prepared using a method including dispersing a suspension in which silicon-based nanoparticles and water-soluble polymer are added to a solvent using ultrasonic waves; and preparing a core including the silicon-based nanoparticles having the polymer carbides on the surface by carbonizing the water-soluble polymer. As a result, a negative electrode active material having a significantly low volume expansion rate compared with general non-carbon-based negative electrode active materials, and having excellent electric conductivity may be provided.
    Type: Application
    Filed: November 27, 2015
    Publication date: October 26, 2017
    Applicant: LG Chem, Ltd.
    Inventors: Hyun Chul Kim, Yong Ju Lee, Yoon Ah Kang, Eun Kyung Kim
  • Method for reducing size and center positioning of magnetic memory element contacts
    Patent number: 9793467
    Abstract: A method of centering a contact on a layer of a magnetic memory device. In one embodiment, a spacers is formed in an opening surrounding the upper layer and the contact is formed within the spacer. The spacer is formed from an anisotropically etched conformal layer deposited on an upper surface and into the opening.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Yong Ju Lee, Charles C. Kuo, David L. Kencke, Kaan Oguz, Roksana Golizadeh Mojard, Uday Shah
  • MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME
    Publication number: 20170293427
    Abstract: A memory module may include a first memory device configured to be controlled by a host memory controller, to transmit/receive data to/from the host memory controller in a first mode, and to transmit/receive data to/from a module memory controller in a second mode, a second memory device configured to be controlled by the module memory controller and to transmit/receive data to/from the module memory controller in the second mode, and the module memory controller configured to monitor control of the first memory device by the host memory controller, to exchange data such that the data is transmitted/received between the first memory device and the second memory device in the second mode, and to control the second memory device.
    Type: Application
    Filed: August 25, 2016
    Publication date: October 12, 2017
    Inventors: Jung-Hyun KWON, Yong-Ju KIM, Sang-Gu JO, Jae-Sun LEE, Do-Sun HONG, Sung-Eun LEE, Jing-Zhe XU, Dong-Gun KIM
  • Delay circuit
    Patent number: 9787296
    Abstract: A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: October 10, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sung-Eun Lee, Kyung-Hoon Kim, Myeong-Jae Park, Woo-Yeol Shin, Han-Kyu Chi, Yong-Ju Kim
  • MEMORY SYSTEM INCLUDING MEMORY CONTROLLER AND OPERATION METHOD THEREOF
    Publication number: 20170285942
    Abstract: A memory system may include a memory device suitable for storing data requested from a host, and a controller suitable for generating information on the data and transmitting/receiving the data and the information to/from the memory device through first and second data buses, respectively, during a first operation mode, or for transmitting/receiving the data to/from the memory device through one of the first and second data buses based on the data size, during a second operation mode.
    Type: Application
    Filed: September 20, 2016
    Publication date: October 5, 2017
    Inventors: Hyung-Gyun YANG, Yong-Ju KIM, Hong-Sik KIM
  • Anode active material for lithium secondary battery, method of preparing the same, and lithium secondary battery including the same
    Patent number: 9780367
    Abstract: Disclosed herein is a non-carbon-based anode active material for lithium secondary batteries, including: a core containing silicon (Si); and silicon nanoparticles formed on the surface of the core. The non-carbon-based anode active material is advantageous in that the increase in the volume expansion during charging-discharging can be prevented by the application of silicon nanoparticles, and in that SiOx(x<1.0) can be easily prepared.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: October 3, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Je-Young Kim, Hyun-Chul Kim, Yong-Ju Lee
  • Water tank for floating-type humidifier
    Patent number: D800285
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: October 17, 2017
    Assignee: INTELLECTUAL DISCOVERY CO., LTD.
    Inventors: Dong Jin Seo, Yong Ju Oh, Min Seok Kim