Abstract: A memory system may include a first memory having a first operating speed, and a second memory having a second operating speed which is different from the first operating speed. A compression device may compress data of the first memory, and may transfer the compressed data to the second memory. The compression device may select a compression scheme among a plurality of compression schemes based on at least one characteristic of the data of the first memory and a data processing combination selected among a plurality of data processing combinations between a series of data processing units of the first memory and a series of data processing units of the second memory, and may compress the data of the first memory according to the selected compression scheme.

Abstract: A memory network includes a first local memory group, a second local memory group, and multiple first channels. The first local memory group includes multiple first memory devices that are not directly connected to each other. The second local memory group includes multiple second memory devices that are not directly connected to each other. The first channels are configured to connect the first memory devices to the second memory devices in a one to one relationship.

Abstract: A semiconductor device includes: a first memory chip including a plurality of first memory regions; a temporary memory chip including a plurality of temporary memory regions; and a control chip suitable for accessing a first access target memory region among the plurality of first memory regions or a first temporary memory region among the plurality of temporary memory regions based on first access information and first temperature readout information corresponding to the plurality of first memory regions.

Abstract: A system includes a central processing unit (CPU); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the CPU and the plurality of memory ports; and a memory controller suitable for, when the CPU calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.

Abstract: A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.

Abstract: A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set.

Abstract: A memory controller schedules requests to memory devices according to scores. For this purpose, the memory controller variably adjusts weights for determining the scores with respect to the requests, calculates the scores using the weights, and determines a processing order of the requests according to the scores. The memory controller includes a request queue, a scheduler, and a weight generation circuit. The request queue stores the requests provided from an external device. The scheduler calculates a score for each request included in the request queue and determines the processing order of the requests based on the scores for the requests. The weight generation circuit generates a weight vector including the weights used to calculate the scores.

Abstract: A system includes a central processing unit (CPU); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the CPU and the plurality of memory ports; and a memory controller suitable for, when the CPU calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.

Abstract: A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes.

Abstract: A memory system may include a first memory having a first operating speed, and a second memory having a second operating speed which is different from the first operating speed. A compression device may compress data of the first memory, and may transfer the compressed data to the second memory. The compression device may select a compression scheme among a plurality of compression schemes based on at least one characteristic of the data of the first memory and a data processing combination selected among a plurality of data processing combinations between a series of data processing units of the first memory and a series of data processing units of the second memory, and may compress the data of the first memory according to the selected compression scheme.

Abstract: A semiconductor device includes: a first memory chip including a plurality of first memory regions; a temporary memory chip including a plurality of temporary memory regions; and a control chip suitable for accessing a first access target memory region among the plurality of first memory regions or a first temporary memory region among the plurality of temporary memory regions based on first access information and first temperature readout information corresponding to the plurality of first memory regions.

Abstract: A memory network includes a first local memory group, a second local memory group, and multiple first channels. The first local memory group includes multiple first memory devices that are not directly connected to each other. The second local memory group includes multiple second memory devices that are not directly connected to each other. The first channels are configured to connect the first memory devices to the second memory devices in a one to one relationship.

Abstract: A data storage device may include: a data storage unit comprising a plurality of channels each having a plurality of nonvolatile memory devices; and a control unit configured to control a garbage collection operation of selecting a first block included in a first channel as a victim block and copying first data included in the first block into a second block included in a second channel that is selected.

Abstract: A memory system may include a memory module including a plurality of memory devices suitable for storing a data word containing multi-bit data, and a memory controller suitable for controlling a write operation and a read operation of the memory module and distributing and mapping the data word to the plurality of memory devices, wherein as a memory device has a higher error occurrence count among the memory devices, the controller maps higher-significant bits of the multi-bit data to the memory device.

Abstract: An operation method of a memory device includes: receiving a computation command; receiving a first address corresponding to the computation command; reading first data from a first memory location designated by the first address; receiving a second address corresponding to the computation command; reading second data from a second memory location designated by the second address; and performing a computation operation corresponding to the computation command on the first and second data.

Abstract: A memory controller includes: a write performance storage circuit suitable for storing write performance indexes of physical memory areas of a memory device, a write counting circuit suitable for counting a number of requests of a write operation on logical memory areas of the memory device, and a mapping circuit suitable for mapping a logical memory area, for which the number of requests of the write operation r may be relatively large, to a physical memory area with a better write performance index.

Abstract: A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array.

Abstract: A semiconductor device remaps the relationship between logical addresses and physical addresses of a semiconductor memory device at each first interval. The semiconductor device may include a wear leveling controller configured to select a first physical address of the semiconductor memory device to remap a logical address corresponding to the first physical address of the semiconductor memory device to a second physical address of the semiconductor memory device, and to adjust the first interval.

Abstract: A memory controller includes a request queue that stores requests provided from an external device, a scheduler that calculates a score for each request included in the request queue and determines a processing order of the requests based on the scores for the requests, and a weight generation circuit that generates a weight vector including weights used to calculated the scores.

Abstract: A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.