Abstract: An input buffer of the present invention has dual paths for increasing input signal processing speed by using two input buffers having input characteristics that differ from each other. The input buffer includes an input terminal receiving an external input signal; and first and second input buffers, both coupled to the input terminal for transferring an external input signal. The output signal of the second input buffer is blocked when the first input buffer transfers the external input signal, and the output signal of the first input buffer is blocked when the second input buffer transfers the external input signal.

Abstract: A high voltage detector used in an integrated circuit having a high voltage generator for generating high voltage boosting internal voltage is disclosed. The high voltage detector may include a reference voltage supply for supplying reference voltage and a low voltage detector for comparing the reference voltage and the internal voltage and generating a low voltage detecting signal, which is enabled when the internal voltage level is less than a predetermined voltage level. The high voltage detector may also include a control signal outputting unit, which is configured as a current mirror and the high voltage and the internal voltage are applied, for controlling current flowing through the current mirror in response to the low voltage detecting signal and outputting a pumping control signal having a first or a second potential level.

Abstract: An input buffer of the present invention has dual paths for increasing input signal processing speed by using two input buffers having input characteristics that differ from each other. The input buffer includes an input terminal receiving an external input signal; and first and second input buffers, both coupled to the input terminal for transferring an external input signal. The output signal of the second input buffer is blocked when the first input buffer transfers the external input signal, and the output signal of the first input buffer is blocked when the second input buffer transfers the external input signal.

Abstract: The present invention discloses an input buffer which can improve the properties of a setup time and a hold time of an input signal. When the setup time is important, a path of a short delay time is employed, and when the hold time is important, a path of a long delay time is used. Therefore, the internal setup time/hold time may be suitably selected in the system application conditions. For this, the input buffer includes: a buffer for receiving a signal through an input pin; a plurality of delay units for delaying the signal inputted from the buffer by a different delay time; and a selecting unit for selectively outputting one of the output signals from the plurality of delay units according to an externally-inputted reference signal and the logic variation of the input signal from the buffer.

Abstract: A semiconductor memory device, comprising: address input means for receiving an external column address signal; address buffer means for converting the external column address signal through address input terminal into an internal column address signal; address predecoder means for receiving the internal column address signal from the address buffer means and predecoding it to generate global column address signals; column redundancy fuse array means for generating a first detection signal indicating whether the global column address signals are normal address signals or spare address signals and a second detection signal indicating that the defects are fully repaired with any one of a column redundancy circuit or a row redundancy circuit; redundancy selection means for generating a spare column enable signal or a normal column enable signal in accordance with the first detection signal; address block repeater means for directly providing the global column address signals from the predecoder as column address

Abstract: An on-chip voltage generating device for semiconductor memory which generates a higher voltage than a power supply voltage or a lower voltage than a ground voltage is provided. The on-chip voltage generating device comprises an on-chip voltage generater for outputting the on-chip voltage by a pumping operation, an on-chip voltage detector for receiving the on-chip voltage, the on-chip voltage detector detecting the voltage level of the on-chip voltage and controlling the operation of the on-chip voltage generater; and an oscillator for controlling an operation of the on-chip voltage detector.

Abstract: An exposure apparatus includes a frame member with a first stage having a substrate disposed thereon provided in a lower portion of the frame member. A leveling mechanism is provided for adjusting an orientation of the first stage. The exposure apparatus further includes a second stage positioned over the first stage and fixed to the frame member. A reticle is positioned on the second stage. An exposure area limiting mechanism is provided in the exposure apparatus and positioned over the second stage. The exposure area limiting mechanism defines an opening through which light is capable of passing during exposure for limiting an exposure area of the second stage. The exposure apparatus also includes an illumination system to irradiate light to the exposure area limiting means.

Abstract: Disclosed is a semiconductor memory device with a reduced consumption of standby current in a self-refresh mode. The semiconductor memory device includes a DC voltage source control circuit unit for controlling a DC voltage generating unit. The DC voltage source control unit periodically turns on and off the DC voltage generating unit in such a fashion that voltages sources used for a self-refresh operation are maintained their OFF states during standby in a self-refresh mode.

Abstract: A lamp arc observing apparatus includes a lens unit installed in the path of light emitted from a lamp, a camera for viewing the image of the electrodes of the lamp through the lens unit, and a light intensity controlling device installed between the lens unit and the camera for controlling the intensity of light incident on the camera so that the camera can capture the image of the electrodes of the lamp.

Abstract: A holographic screen of a rear projection type for use in a projector for transmitting projection light received from a rear end of the projector onto a viewing surface. The holographic screen includes a holographic sheet including a viewing surface for forming the received projection light into an image viewing, a plurality of diffusion protrusions disposed on the viewing surface in predetermined intervals along horizontal and vertical directions of the viewing surface for diffusing incident projection light, and a plurality of scattering protrusions formed over the entire viewing surface for scattering the received projection light, and a plurality of light absorbers formed between the plurality of protrusions, for absorbing ambient light incident to the viewing surface. Thus, an image with improved contrast is displayed on a viewing surface of the holographic screen.

Abstract: A buffer control circuit and method for a semiconductor memory device with a power saving function power saving function. The buffer control circuit includes an internal clock signal generator for generating an internal clock signal in response to an external clock signal, an internal chip select signal generator for generating an internal chip select signal in response to an external chip select signal, a buffer control signal generator for combining the internal clock signal from the internal clock signal generator and the internal chip select signal from the internal chip select signal generator to generate a buffer control signal, a command/address buffering circuit operative in response to the buffer control signal from the buffer control signal generator, for storing external input command and address, and a decoder for decoding commands from the command/address buffering circuit.

Abstract: A power line noise prevention circuit for a semiconductor memory device which can suppress noises on supply and ground voltage lines with no conventional degradation in operation speed when internal circuits consuming a large current amount are sequentially operated. When a plurality of data output buffers output high data at the same time, the power line noise prevention circuit applies a high voltage to the supply voltage line for the operation time to prevent a supply voltage from being reduced in level. To the contrary, when a plurality of data output buffers output low data at the same time, the power line noise prevention circuit applies a substrate voltage to the ground voltage line for the operation time to prevent a ground voltage from being increased in level.

Abstract: A holographic screen of a rear projection type for use in a projector for transmitting projection light received from a rear end of the projector onto a viewing surface. The holographic screen includes a holographic sheet having an incident surface for receiving projection light, a viewing surface for forming the projection light received by the incident surface into a viewable image, a plurality of protrusions disposed in parallel with each other for scattering the received projection light; and a plurality of light absorbers which are formed between the plurality of the protrusions on the viewing surface, for absorbing ambient light incident to the viewing surface. Thus, an image whose contrast is improved is displayed on a viewing surface.

Abstract: Disclosed herein is make-up cosmetic compositions containing powdered Phaffia yeast.According to the present invention, the make-up cosmetic composition contains the powdered Phaffia yeast in an amount of 0.1 to 50% by weight based on the total amount of the composition. Said powdered Phaffia yeast is prepared by sterilizing Phaffia yeast by radiation sterilization or compressed steam sterilization, and then spray-drying the suspension containing the sterilized yeast. The Phaffia yeast employed in the present invention are Phaffia rhodozyma, astaxanthin-producing mutants, .beta.-carotane-accumulating mutants and white carotenoid pigments-producing mutants, of Phaffia rhodozyma.