Abstract: A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.

Abstract: An equipment and method to classify semiconductor packages diced on a substrate into defective and non-defective semiconductor packages includes a loading preparation table to receive a plurality of semiconductor packages to be inspected, a first inspection unit to inspect and classify the semiconductor packages received at the loading preparation table into normal semiconductor packages and defective semiconductor packages, a temporary loading table to temporarily receive at least a portion of the normal semiconductor packages, a first loading picker to transfer the defective semiconductor packages from the loading preparation table to a defective package loading tray and to transfer the normal semiconductor packages from the temporary loading table to the loading preparation table, and a second loading picker to transfer the normal semiconductor packages from the loading preparation table to a normal package loading tray.

Abstract: A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system.

Abstract: An on die thermal sensor (ODTS) of a semiconductor memory device includes a high voltage generating unit for generating a high voltage having a voltage level higher than that of a power supply voltage of the semiconductor memory device; and a thermal information output unit for sensing and outputting a temperature as a thermal information code, wherein the thermal information output unit uses the high voltage as its driving voltage.

Abstract: An on die thermal sensor (ODTS) of a semiconductor memory device includes a high voltage generating unit for generating a high voltage having a voltage level higher than that of a power supply voltage of the semiconductor memory device; and a thermal information output unit for sensing and outputting a temperature as a thermal information code, wherein the thermal information output unit uses the high voltage as its driving voltage.

Abstract: A fuel cell system includes a fuel cell system connector and a fuel cartridge connector. The fuel cell system connector includes an external structure configured to accommodate a connector of a fuel cartridge and an internal structure mounted in the external structure. A contacting surface between the external structure and the internal structure of the fuel cell system connector includes a first nano-processed surface on a fuel supply path. The fuel cartridge connector includes an external structure having a retention key and an internal structure mounted in the external structure. A contacting surface between the external structure and the internal structure of the fuel cartridge connector includes a second nano-processed surface on a fuel supply path.

Abstract: A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a precharge operation in response to the reset entry signal and a refresh operation in response to the reset exit signal.

Abstract: A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.

Abstract: The present invention relates to device and method for adjusting white balance in a laser display system, which enables to adjust white balance taking an optical characteristic of a laser beam into account.

Abstract: A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addresses. The data input/output line transfers data with a cell array. The selecting unit selectively outputs the buffered addresses transferred from the address buffering unit and the data transferred through the data input/output line according to modes of the device. The output circuit latches an output of the selecting unit to be outputted from the device.

Abstract: A dynamic random access memory includes: an address latch configured to latch a row address in response to a row address strobe (RAS) signal and latch a column address in response to a column address strobe (CAS) signal; a row decoder configured to decode the row address; an enabler configured to decode a part of most significant bits (MSB) of the column address to locally enable a part of one page area corresponding to the row address; and a column decoder configured to decode the column address.

Abstract: A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a precharge operation in response to the reset entry signal and a refresh operation in response to the reset exit signal.

Abstract: A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a precharge operation in response to the reset entry signal and a refresh operation in response to the reset exit signal.

Abstract: A dual in-line memory module (DIMM) for use in test includes a memory array with a plurality of memories, a test signal input/output unit, and a normal data input/output unit. The test signal input/output unit is provided in the respective memories to perform an input/output operation of a test signal with an external test mode controller for a test mode operation. The normal data input/output unit is provided in the respective memories to perform an input/output operation of a normal data with an external memory controller for a normal mode operation.

Abstract: A semiconductor memory device is presented that exhibits an enhanced read/write data retrieval efficiency brought about in part by a uniquely shared column array communication scheme. The semiconductor memory device includes: at least one group of banks, the banks being disposed adjacent to each other to form a radially symmetrical arrangement of banks having a row and column geometry; and a column decoder array is positioned between pairs of vertically disposed banks in which the column decoder array communicates with this pair of vertically disposed banks so that a single column select signal from the column decoder array can be used to select a given memory cell of the one bank of this vertically disposed banks.

Abstract: A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.

Abstract: A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addresses. The data input/output line transfers data with a cell array. The selecting unit selectively outputs the buffered addresses transferred from the address buffering unit and the data transferred through the data input/output line according to modes of the device. The output circuit latches an output of the selecting unit to be outputted from the device.

Abstract: A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.

Abstract: A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.

Abstract: A semiconductor memory device is presented that exhibits an enhanced read/write data retrieval efficiency brought about in part by a uniquely shared column array communication scheme. The semiconductor memory device includes: at least one group of banks, the banks being disposed adjacent to each other to form a radially symmetrical arrangement of banks having a row and column geometry; and a column decoder array is positioned between pairs of vertically disposed banks in which the column decoder array communicates with this pair of vertically disposed banks so that a single column select signal from the column decoder array can be used to select a given memory cell of the one bank of this vertically disposed banks.