Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

Abstract: An image encoding/decoding method and apparatus for performing intra prediction using a plurality of reference sample lines are provided. An image decoding method may comprise configuring a plurality of reference sample lines, reconstructing an intra prediction mode of a current block, and performing intra prediction for the current block based on the intra prediction mode and the plurality of reference sample lines.

Abstract: Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

Abstract: Disclosed herein is a video decoding method including: obtaining a transform skip mode flag indicating whether or not a transform skip mode is applied to a current block; based on the transform skip mode flag, when a transform skip mode is applied to the current block, determining that secondary transform/inverse transform is not applied to the current block; and, according to the transform skip mode flag, when a transform skip mode is not applied to the current block, obtaining a transform matrix index for secondary transform/inverse transform of the current block and, according to the transform matrix index, determining whether or not secondary transform/inverse transform is applied to the current block.

Abstract: One embodiment of the present disclosure relates to a secondary battery module. A secondary battery module includes a plurality of battery cells and a first frame configured to accommodate and cool the plurality of battery cells. The first frame includes a housing configured to accommodate the plurality of battery cells and at least one cooling plate coupled to one surface of the housing, interposed between groups of one or more battery cells among the plurality of battery cells disposed in the housing, and configured to fix the plurality of battery cells and dissipate heat generated from the plurality of battery cells.

Abstract: This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input/output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.

Abstract: A radiometer for a microwave receiver according to an embodiment of the present invention comprises: an antenna line through which radiation power corresponding to the temperature of a probe is received from an antenna; a first reference rod having a first reference temperature fixed in advance; a second reference rod having a second reference temperature fixed in advance; a first microwave switch for selectively switching the antenna line, the first reference load, and the second reference load; a second microwave switch switched with the same clock as the first microwave switch; a demodulator for multiplying a signal output from the second microwave switch by a predetermined gain value and outputting same; an integrator for integrating the signal output from the demodulator; and a controller for measuring the temperature of the probe on the basis of a signal output from the integrator.

Abstract: Disclosed herein is a video decoding method including: obtaining a transform skip mode flag indicating whether or not a transform skip mode is applied to a current block; based on the transform skip mode flag, when a transform skip mode is applied to the current block, determining that secondary transform/inverse transform is not applied to the current block; and, according to the transform skip mode flag, when a transform skip mode is not applied to the current block, obtaining a transform matrix index for secondary transform/inverse transform of the current block and, according to the transform matrix index, determining whether or not secondary transform/inverse transform is applied to the current block.

Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

Abstract: An information handling system detects facial landmarks of a user based on a face detection learning model, and estimates a head pose of the user based on the detected facial landmarks. The system determines adjustment information based on the head pose of the user, and if the head pose of the user is rotated at an angle, then provides audible guidance based on the adjustment information.

Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode, and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell surrounding at least a portion of the core, and a second shell surrounding at least a portion of the first shell, and a concentration of a rare earth element included in the second shell is more than 1.3 times to less than 3.8 times a concentration of a rare earth element included in the first shell.

Abstract: Disclosed is a substrate processing apparatus having a symmetrical reaction space in which a process is performed after a substrate is transferred into the reaction space. The substrate processing apparatus may include: a chamber including a reaction space having an opening formed at one or more sidewalls; and a valve configured to open/close the opening. The valve may include: a blade housed in the chamber including the sidewall and a chamber bottom, which form the reaction space, and configured to open/close the opening; and a driving unit configured to raise and lower the blade, wherein one surface of the blade is formed as the same plane as the inner surface of the chamber by the closing of the opening.

Abstract: There is provided an video encoding/decoding method and apparatus. The video decoding method comprises acquiring a bitstream including a predetermined context element, performing at least one of a context model determination, a probability update, and a probability interval determination on the predetermined syntax element, and arithmetically decoding the predetermined syntax element on the basis of a result of the performance.

Abstract: Provided is a fingerprint authentication device comprising a biometric sensor that senses biometric information to generate a sensing signal; an image processor that extracts a calibration function based on calibration data and generates a fingerprint image based on the calibration function and the sensing signal; and an authenticator that performs fingerprint authentication by comparing the fingerprint image and registered fingerprint information. The calibration data includes information on a calibration coefficient of the calibration function.

Abstract: The present invention relates to an image encoding/decoding method and apparatus. The image decoding method according to the present invention may comprise configuring an MPM list based on intra-prediction modes of neighbor blocks of a current block and a number of frequencies of the intra-prediction modes of the neighbor blocks, deriving an intra-prediction mode of the current block based on the MPM list, and performing intra-prediction for the current block based on the intra-prediction mode.

Abstract: A method and a device for encoding/decoding images are disclosed. The method for encoding images comprises the steps of: deriving a scan type of a residual signal for a current block according to whether or not the current block is a transform skip block; and applying the scan type to the residual signal for the current block, wherein the transform skip block is a block to which transform for the current block is not applied and is specified on the basis of information indicating whether or not transform for the current block is to be applied.

Abstract: Aspects of the disclosed technology include techniques, a mechanism, and an apparatus for diagnosing a battery. One or more processors may measure voltages of a plurality of batteries and, based on the measured voltages, determine a voltage deviation of the plurality of batteries. The one or more processors may determine a voltage deviation variation of each battery of the plurality of batteries at predetermined times periods and may compare a pattern of the voltage deviation variations of each battery of the plurality of batteries with a preset diagnosis pattern to diagnose a state of each of the plurality of batteries.

Abstract: Aspects of the disclosed technology include techniques, a mechanism, and an apparatus for diagnosing a battery. One or more processors may measure voltages of a plurality of batteries and, based on the measured voltages, determine a voltage deviation of the plurality of batteries. The one or more processors may determine a voltage deviation variation of each battery of the plurality of batteries at predetermined times periods and may compare a pattern of the voltage deviation variations of each battery of the plurality of batteries with a preset diagnosis pattern to diagnose a state of each of the plurality of batteries.

Abstract: Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.