Abstract: An anti-seismic reinforcement structure using a panel zone reinforcing fixture, according to the present invention, comprises: panel zone reinforcing fixtures which are coupled, to reinforce an existing frame consisting of a column and a beam as existing members, to one side of the frame and which are respectively fixed to sides of the column and the beam at a panel zone where the existing column and the existing beam are joined to each other; a reinforcing column which is installed at one side of the column and has opposite ends thereof fixed to the panel zone reinforcing fixtures; and a reinforcing beam which is installed at one side of the beam and has opposite ends thereof fixed to the panel zone reinforcing fixtures.

Abstract: The present invention relates to a catalyst for hydrogenation of an aromatic compound, which is capable of greatly reducing the inactivation of a catalyst by using a support including a magnesium-based spinel structure, and a preparation method therefor.

Abstract: Apparatuses and techniques for implementing a data-transfer test mode are described. The data-transfer test mode refers to a mode in which the transfer of data from an interface die to a linked die can be tested prior to connecting the interface die to the linked die. In particular, the data-transfer test mode enables the interface die to perform aspects of a write operation and output a portion of write data that is intended for the linked die. With the data-transfer test mode, testing (or debugging) of the interface die can be performed during an earlier stage in the manufacturing process before integrating the interface die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the data-transfer test mode can be executed independent of whether the interface die is connected to the linked die.

Abstract: The present invention relates to a toothbrush type recommendation apparatus. The toothbrush type recommendation apparatus comprises: a user input unit; an output unit; and an operation control unit connected to the user input unit and the output unit.

Abstract: The present invention relates to an antenna apparatus, particularly comprising: an antenna housing portion which has a predetermined installation space formed therein and is provided with a plurality of front heat dissipation fins protruding to at least one side of the front surface thereof; a main board which is stacked on the installation space of the antenna housing portion and has predetermined heating elements arranged on the front surface thereof, and is mounted to be in thermal contact with the front surface of the antenna housing portion provided with the plurality of front heat dissipation fins; a plurality of filters which form a predetermined layer in front of the main board, and are stacked in a middle portion except for the portion where the plurality of front heat dissipation fins are formed; an antenna element assembly including a plurality of radiation elements stacked in front of the plurality of filters; and an installation plate which is fixed to be in face-to-face contact with the rear sur

Abstract: An image encoding/decoding method and apparatus for performing intra prediction mode based intra prediction are provided. An image decoding method may comprise decoding an intra prediction mode of a current block, deriving at least one intra prediction mode from the decoded intra prediction mode of the current block, generating two or more intra prediction blocks using the intra prediction mode of the current block and the derived intra prediction mode, and generating an intra prediction block of the current block based on the two or more intra prediction blocks.

Abstract: An image encoding/decoding method and apparatus for performing intra prediction mode based intra prediction are provided. An image decoding method may comprise decoding an intra prediction mode of a current block, deriving at least one intra prediction mode from the decoded intra prediction mode of the current block, generating two or more intra prediction blocks using the intra prediction mode of the current block and the derived intra prediction mode, and generating an intra prediction block of the current block based on the two or more intra prediction blocks.

Abstract: Apparatuses and techniques for implementing a standalone mode are described. The standalone mode refers to a mode in which a die that is designed to operate as one of multiple dies that are interconnected can operate independently of another one of the multiple dies. Prior to connecting the die to the other die, the die can perform a standalone read operation and/or a standalone write operation in accordance with the standalone mode. In this way, testing (or debugging) can be performed during an earlier stage in the manufacturing process before integrating the die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the standalone mode can be executed independent of whether the die is connected to the other die.

Abstract: This document describes apparatuses and techniques for die-based rank management for a memory system. In various aspects, a die-based rank controller (controller) can determine which memory dies of a memory device are not functional to store data and correlate rank selections of a memory system to ranks of other memory dies (e.g., functional memory dies). The controller may store information that indicates the correlation or mapping of the rank selections to the ranks of the other memory dies to enable access to those ranks of the memory system. In some aspects, the controller receives a command to access the memory device with a rank selection, and the controller enables access to a corresponding rank based on the information. By so doing, aspects of die-based rank management enable memory packages with non-functional memory dies to be used instead of discarded, which can increase production utilization or lower manufacturing costs.

Abstract: The present invention discloses an image decoding method, the method including generating a candidate list including motion information derived from a spatial neighboring block and a temporal neighboring block adjacent to a current block; deriving motion information of the current block using the candidate list; generating a prediction block of the current block using the derived motion information; and updating the derived motion information in a motion information list, wherein the generating of the candidate list is performed in such a manner as to include at least one information of the motion information included in the updated motion information list in a block decoded before the current block.

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Abstract: An image encoding/decoding method and apparatus for performing representative sample-based intra prediction are provided. An image decoding method may comprise deriving an intra prediction mode of a current block, configuring a reference sample of the current block, and performing intra prediction for the current block based on the intra prediction mode and the reference sample, wherein the intra prediction is representative sample-based prediction.

Abstract: Systems, apparatuses, and methods related to a memory device and an associated host device are described. The memory device and the host device can include control logic that allow the memory device and host device to share refresh-timing information, which may allow either the memory device or the host, or both, to manage operations during time that is dedicated to, but unused for, refresh or self-refresh operations. Refresh-timing information shared from the host device may indicate elapsed time since the host device issued a refresh command to the memory device and/or how much time remains before the host device is scheduled to issue another refresh command. Refresh-timing information shared from the memory device may indicate elapsed time since the memory device performed a self-refresh operation and/or how much time remains before the memory device is scheduled to initiate or undergo another self-refresh operation.

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Abstract: A display apparatus includes: a display panel including a display area, and a pad area adjacent to the display area; and a circuit board attached to the pad area. The pad area includes at least one signal pad terminal electrically connected to a first signal line extending through the display area, and at least one dummy pad terminal spaced from the first signal line. The circuit board includes a signal lead terminal connected to the signal pad terminal, and a dummy lead terminal connected to the dummy pad terminal.

Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.

Abstract: Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.

Abstract: A hinge includes a first shaft and a second shaft that are parallel to each other, first and third arms rotatably coupled to the first shaft and including first and third rotary cams, second and fourth arms rotatably coupled to the second shaft and including second and fourth rotary cams, a first sliding part coupled to the first and second shafts to be movable along the first and second shafts and including a first sliding cam facing the first rotary cam and a second sliding cam facing the second rotary cam, a second sliding part coupled to the first and second shafts to be movable along the first and second shafts and including a third sliding cam facing the third rotary cam and a fourth sliding cam facing the fourth rotary cam, and an elastic member disposed between the first sliding part and the second sliding part.

Abstract: Disclosed is a method of decoding an image and a method of encoding an image. The method of decoding an image includes: obtaining motion-constrained tile set information; determining, on the basis of the motion-constrained tile set information, a first boundary region of a collocated tile set within a reference picture, which corresponds to a motion-constrained tile set; padding a second boundary region corresponding to the first boundary region; and performing inter prediction on the motion-constrained tile set by using a collocated tile set that includes the padded second boundary region.