Patents by Inventor Yong-kuk Jeong

Yong-kuk Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200157427
    Abstract: The present invention relates to a liquid crystal (LC) medium comprising a terphenyl compound and at least two polymerisable compounds, to a process for its preparation, to its use for optical, electro-optical and electronic purposes, in particular in LC displays, especially in an LC display of the polymer sustained alignment (PSA) type, and to an LC display, especially a PSA display, comprising it.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 21, 2020
    Applicant: MERCK PATENT GMBH
    Inventors: Hyun-Jin YOON, Ji-Won JEONG, Eun-Kyu LEE, Min-Ok JIN, Yong-Kuk YUN
  • Patent number: 10557083
    Abstract: The present invention relates to a liquid crystal (LC) medium comprising a terphenyl compound and at least two polymerisable compounds, to a process for its preparation, to its use for optical, electro-optical and electronic purposes, in particular in LC displays, especially in an LC display of the polymer sustained alignment (PSA) type, and to an LC display, especially a PSA display, comprising it.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: February 11, 2020
    Assignee: MERCK PATENT GMBH
    Inventors: Hyun-Jin Yoon, Ji-Won Jeong, Eun-Kyu Lee, Min-Ok Jin, Yong-Kuk Yun
  • Patent number: 8951853
    Abstract: A method of forming a semiconductor device includes forming a gate electrode and source/drain regions in a semiconductor substrate, forming a first capping nitride layer covering the gate electrode and the source/drain regions, the first capping nitride layer including a Si—H rich SiN layer, annealing the semiconductor substrate having the first capping nitride layer, and removing the first capping nitride layer.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pan-Kwi Park, Dong-Suk Shin, Yong-Kuk Jeong, Dong-Hyun Roh, Ha-Jin Lim
  • Patent number: 8790972
    Abstract: Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen plasma. A tensile stress layer may be formed on the PMOS transistor. The exposing step may include exposing source and drain regions of the PMOS transistor to the hydrogen plasma.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: July 29, 2014
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, GLOBALFOUNDRIES Singapore Pte. Ltd., Freescale Semiconductor, Inc.
    Inventors: Yong-Kuk Jeong, Laegu Kang, Kim Nam Sung, Dae-won Yang
  • Patent number: 8648408
    Abstract: A semiconductor device includes a substrate, a gate structure disposed on the substrate and which includes a gate insulating layer and a gate electrode layer, a first nitride layer disposed on the substrate and the gate structure and which includes silicon, and a second nitride layer that is disposed on the first nitride layer and has an atomic percentage of silicon less than that of the first nitride layer.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kuk Jeong, Sang-Wook Park, Min-Hee Choi
  • Patent number: 8361852
    Abstract: A transistor includes a silicon germanium channel layer formed on a portion of a single crystalline silicon substrate. The silicon germanium channel layer includes a Si—H bond and/or a Ge—H bond at an inner portion or an upper surface portion thereof. A PMOS transistor is provided on the silicon germanium channel layer. A silicon nitride layer is provided on surface portions of the single crystalline silicon substrate, the silicon germanium channel layer and the PMOS transistor for applying a tensile stress. The MOS transistor shows good operating characteristics.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yong-Kuk Jeong
  • Patent number: 8237202
    Abstract: Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: August 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-kuk Jeong, Andrew-tae Kim, Dong-suk Shin
  • Publication number: 20120045873
    Abstract: Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen plasma. A tensile stress layer may be formed on the PMOS transistor. The exposing step may include exposing source and drain regions of the PMOS transistor to the hydrogen plasma.
    Type: Application
    Filed: August 19, 2010
    Publication date: February 23, 2012
    Inventors: Yong-Kuk Jeong, Laegu Kang, Kim Nam Sung, Dae-won Yang
  • Publication number: 20110306198
    Abstract: A method of fabricating a semiconductor integrated circuit device includes forming a gate pattern on a semiconductor substrate, the gate pattern having a gate insulation film and a gate electrode. A spacer is formed on sidewalls of the gate pattern. A silicide layer is formed by a silicide process on at least one portion of the semiconductor substrate exposed by the gate pattern and the spacer, the silicide layer being formed using a silicide process. A stress buffer layer is formed on a resultant structure having the silicide layer. A stress film is formed on the stress buffer layer.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 15, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Kuk Jeong, Dong-Suk Shin, Jong-Hun Kim, Hyun-Kwan Yu, Ki-eun Kim
  • Publication number: 20110207273
    Abstract: A transistor includes a silicon germanium channel layer formed on a portion of a single crystalline silicon substrate. The silicon germanium channel layer includes a Si—H bond and/or a Ge—H bond at an inner portion or an upper surface portion thereof. A PMOS transistor is provided on the silicon germanium channel layer. A silicon nitride layer is provided on surface portions of the single crystalline silicon substrate, the silicon germanium channel layer and the PMOS transistor for applying a tensile stress. The MOS transistor shows good operating characteristics.
    Type: Application
    Filed: December 29, 2010
    Publication date: August 25, 2011
    Inventor: Yong-Kuk Jeong
  • Publication number: 20110163386
    Abstract: Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
    Type: Application
    Filed: January 10, 2011
    Publication date: July 7, 2011
    Inventors: Yong-kuk Jeong, Andrew-tae Kim, Dong-suk Shin
  • Patent number: 7888749
    Abstract: A semiconductor device includes an active region. A gate electrode is disposed on the active region. An isolation region adjoins the active region, and is recessed with respect to a top surface of the active region underlying the gate electrode. The isolation region may be recessed a depth substantially equal to a height of the gate electrode. In some embodiments, the gate electrode is configured to support current flow through the active region along a first direction, and a tensile stress layer covers the gate electrode and is configured to apply a tensile stress to the gate electrode along a second direction perpendicular to the first direction. The tensile stress layer may cover the recessed isolation region and portions of the active region between the isolation region and the gate electrode. In further embodiments, an interlayer insulating film is disposed on the tensile stress layer and is configured to apply a tensile stress to the gate electrode along the second direction.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-suk Shin, Andrew Tae Kim, Yong-kuk Jeong
  • Patent number: 7867867
    Abstract: Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: January 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-kuk Jeong, Andrew-tae Kim, Dong-suk Shin
  • Patent number: 7868421
    Abstract: Analog capacitors, and methods of fabricating the same, include a lower electrode having a lower conductive layer, a capacitor dielectric layer on the lower conductive layer, and an upper electrode on the capacitor dielectric layer to be opposite to the lower electrode, wherein the upper electrode includes at least an upper conductive layer in contact with the capacitor dielectric layer, wherein the upper conductive layer has a resistivity higher than that of the lower conductive layer.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: January 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Yong-Kuk Jeong
  • Patent number: 7863201
    Abstract: Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: January 4, 2011
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Infineon Technologies North America Corp., Infineon Technologies AG
    Inventors: Yong-Kuk Jeong, Bong-Seok Suh, Dong-Hee Yu, Oh-Jung Kwon, Seong-Dong Kim, O Sung Kwon
  • Patent number: 7833580
    Abstract: A method of forming a carbon nano-material layer may involve a cyclic deposition technique. In the method, a chemisorption layer or a chemical vapor deposition layer may be formed on a substrate. Impurities may be removed from the chemisorption layer or the chemical vapor deposition layer to form a carbon atoms layer on the substrate. More than one carbon atoms layer may be formed by repeating the method.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Dae-Jin Kwon, Yong-Kuk Jeong
  • Patent number: 7808043
    Abstract: A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: October 5, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Chul Kim, Dong-Suk Shin, Yong-Kuk Jeong
  • Publication number: 20100197124
    Abstract: A semiconductor integrated circuit device with enhanced reliability is provided. The semiconductor integrated circuit device includes a semiconductor substrate; a gate insulation film that is provided on the semiconductor substrate; a gate electrode that is provided on the gate insulation film; and a sidewall spacer that is provided on side walls of the gate insulation film and the gate electrode and includes, wherein the sidewall spacer has a first sidewall spacer in contact with the gate electrode and a second sidewall spacer formed on the side walls of the first sidewall spacer, and a ratio of an Si—OH area to an Si—O area in at least one of the first and second sidewall spacers is 0.05 or less, as measured by Fourier Transform InfraRed (FTIR).
    Type: Application
    Filed: February 2, 2009
    Publication date: August 5, 2010
    Inventors: Yong-kuk Jeong, Dong-hee Yu, Jong-ho Yang, Seong-dong Kim
  • Patent number: 7732296
    Abstract: In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corres
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: June 8, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-min Park, Seok-jun Won, Min-woo Song, Yong-kuk Jeong, Dae-jin Kwon, Weon-hong Kim
  • Patent number: 7709927
    Abstract: A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-suk Shin, Il-young Yoon, Yong-kuk Jeong, Jung-shik Heo