Abstract: Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

Abstract: Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.

Abstract: A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

Abstract: A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed.

Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer.

Abstract: Analog capacitors, and methods of fabricating the same, include a lower electrode having a lower conductive layer, a capacitor dielectric layer on the lower conductive layer, and an upper electrode on the capacitor dielectric layer to be opposite to the lower electrode, wherein the upper electrode includes at least an upper conductive layer in contact with the capacitor dielectric layer, wherein the upper conductive layer has a resistivity higher than that of the lower conductive layer.

Abstract: In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

Abstract: A semiconductor device includes an active region. A gate electrode is disposed on the active region. An isolation region adjoins the active region, and is recessed with respect to a top surface of the active region underlying the gate electrode. The isolation region may be recessed a depth substantially equal to a height of the gate electrode. In some embodiments, the gate electrode is configured to support current flow through the active region along a first direction, and a tensile stress layer covers the gate electrode and is configured to apply a tensile stress to the gate electrode along a second direction perpendicular to the first direction. The tensile stress layer may cover the recessed isolation region and portions of the active region between the isolation region and the gate electrode. In further embodiments, an interlayer insulating film is disposed on the tensile stress layer and is configured to apply a tensile stress to the gate electrode along the second direction.

Abstract: Provided is a method of manufacturing a semiconductor device with enhancements of electrical characteristics. The method includes sequentially forming a lower electrode and an insulating layer on a semiconductor substrate, dry-etching a region of the insulating layer corresponding to a capacitor forming region so that the lower electrode is not exposed, forming an inter-insulating layer by wet-etching the insulating layer so that a region of the lower electrode corresponding to the capacitor forming region is exposed, and sequentially forming a dielectric layer and an upper electrode on the capacitor forming region to fabricate a capacitor.

Abstract: Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.

Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.

Abstract: There is provided a method of fabricating an analog capacitor using a post-treatment technique. The method includes forming a lower insulating layer on a semiconductor substrate. A bottom electrode is formed on the lower insulating layer, and a capacitor dielectric layer is formed on the bottom electrode. Then, the capacitor dielectric layer is post-treated in a deoxidizing medium. Then, the post-treated capacitor dielectric layer is post-treated in an oxidizing medium. A top electrode is formed on the post-treated capacitor dielectric layer. The analog capacitor fabricated through the post-treatment as above has a low VCC.

Abstract: A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

Abstract: In a method of manufacturing a capacitor of a semiconductor device and an apparatus therefor, dielectric layers are deposited using only a source gas without a reactant gas and a curing process is performed a single time. As a result, process simplification, yield improvement, and equipment simplification are achieved. In a stand-alone memory or an embedded memory, the step coverage is enhanced and oxidation of a storage node contact plug is prevented. Also, in an analog capacitor, an RF capacitor, or a high-voltage capacitor, which uses thicker dielectric layers than the stand-alone capacitor or the embedded capacitor, the manufacturing process is greatly simplified.

Abstract: A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.

Abstract: Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.

Abstract: In a method of manufacturing a capacitor of a semiconductor device and an apparatus therefor, dielectric layers are deposited using only a source gas without a reactant gas and a curing process is performed a single time. As a result, process simplification, yield improvement, and equipment simplification are achieved. In a stand-alone memory or an embedded memory, the step coverage is enhanced and oxidation of a storage node contact plug is prevented. Also, in an analog capacitor, an RF capacitor, or a high-voltage capacitor, which uses thicker dielectric layers than the stand-alone capacitor or the embedded capacitor, the manufacturing process is greatly simplified.

Abstract: Trench isolation methods include forming a first trench and a second trench, having a larger width than the first trench, in a semiconductor substrate. A lower isolation layer is formed having a first thickness on an upper sidewall of the first trench and a second thickness on an upper sidewall of the second trench using a first high density plasma deposition process, the second thickness being greater than the first thickness. An upper isolation layer is formed on the semiconductor substrate including the lower isolation layer using a second high density plasma deposition process, different from the first high density plasma deposition process. The first and second high density plasma deposition processes may be chemical vapor deposition processes. Semiconductor devices including a trench isolation structure are also provided.

Abstract: In a method of fabricating a trench isolation structure of a semiconductor device, excellent gap filling properties are attained, without the generation of defects. In one aspect, the method comprises: loading a substrate with a trench formed therein into a high-density plasma (HDP) chemical vapor deposition apparatus; primarily heating the substrate; applying a first bias power to the apparatus so as to form an HDP oxide liner on side wall and bottom surfaces of the trench, a gap remaining in the trench following formation of the HDP oxide liner; removing the application of the first bias power and secondarily heating the substrate; applying a second bias power at a power level that is greater than that of the first bias power to the substrate so as to form an HDP oxide film to fill the gap in the trench; and unloading the substrate from the apparatus.

Abstract: A method of forming a dielectric layer using a plasma enhanced atomic layer deposition technique includes: loading a semiconductor substrate having a three-dimensional structure into a reaction chamber; and repeatedly performing the following steps until a dielectric layer with a desired thickness is formed: supplying a source gas into the reaction chamber; stopping the supply of the source gas and purging the source gas remaining inside the reaction chamber; and supplying oxygen gas into the reaction chamber after purging the source gas, and applying RF power for oxygen plasma treatment, a level of the applied RF power and a partial pressure of the oxygen gas being increased concurrently with an increased aspect ratio of the three-dimensional structure.