Patents by Inventor Yong Meng

Yong Meng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210141609
    Abstract: A device for generation of genuine random numbers, uses quantum stochastic processes in optical parametric nonlinear media. The dimensionality of the random numbers is varied from 2 to over 100,000. Their statistical properties, including the correlation function amongst random numbers, are tailored using linear and nonlinear optical circuits following the parametric nonlinear media. Both the generation and manipulation of random numbers can be integrated on a single nanophotonics chip. By incorporating optoelectric effects, fast streams of random numbers can be created in custom statistical properties, which can be updated or reconfigured in real time, such as at 10 GHz speed. The unpredictability of the random numbers is quantifying by evaluating their min-entropy. The genuineness of quantum random numbers is tested using both statistical tools and independently verified by measuring the quantum entanglement between the photons in real time reducing vulnerability to hostile attack.
    Type: Application
    Filed: June 27, 2018
    Publication date: May 13, 2021
    Applicant: THE TRUSTEES OF THE STEVENS INSTITUTE OF TECHNOLOGY
    Inventors: Yuping Huang, Yong Meng Sua, Jiayang Chen, Lac Thi Thanh Nguyen
  • Publication number: 20210116543
    Abstract: Approaches, apparatuses and methods for LIDAR applications based on mode-selective frequency conversion are disclosed. In one embodiment, a pulse generation unit includes a mode-locked fiber laser and optical fiber bandpass filters. In the second embodiment, a LIDAR transceiver unit based on a simple, bidirectional monostatic coaxial arrangement using off-the-shelf tele-com-grade optical components includes optical fiber, fiber collimator, optical fiber circulator, optical fiber isolator and wavelength combiner. A frequency conversion detection system with single photon sensitivity includes a nonlinear optical material for frequency conversion, coupled with optimized pump pulses for efficient conversion and noise rejection, optical band pass filters for noise rejection and a single photon detection system for detecting the converted signal.
    Type: Application
    Filed: June 13, 2019
    Publication date: April 22, 2021
    Applicant: THE TRUSTEES OF THE STEVENS INSTITUTE OF TECHNOLOGY
    Inventors: Yuping HUANG, Yong Meng SUA, Amin SHAHVERDI
  • Publication number: 20180168786
    Abstract: A brush head apparatus of a multifunctional oral care tool comprises a pair of transmission rods (5) respectively connected with a pair of brush heads (1). The pair of brush heads (1) are integrally formed by using a food-grade silica gel type of soft material respectively. The pair of brush heads (1) respectively performs a 360-degree rotation in opposite directions. A back of the pair of brush heads (1) is provided with a back-flushing plate (4). An end portion of the transmission rods (5) is lower than an end portion of the brush heads (1). A top portion of the back-flushing plate (4) is lower than a top portion of the brush heads (1).
    Type: Application
    Filed: October 26, 2015
    Publication date: June 21, 2018
    Inventor: Yong MENG
  • Publication number: 20180140405
    Abstract: A back-flushing plate (4) of a multifunctional oral care tool is provided at a back end of brush heads (1) and has an end portion lower than an end portion of the brush heads (1). A pair of brush heads (1) is driven to rotate by a pair of transmission rods (5), such that the brush heads produce a powerful suction flow. Sucked water splashes onto the back-flushing plate and generate a powerful flush flow, thereby attains a goal of flushing the oral waste away. It solves a problem of deep cleaning of furs and also solves a problem of waste liquid, such as tooth-brushing foam, remaining in an oral cavity.
    Type: Application
    Filed: October 26, 2015
    Publication date: May 24, 2018
    Inventor: Yong MENG
  • Patent number: 9607989
    Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xusheng Wu, Yue Hu, Xin Wang, Yong Meng Lee, Wen-Pin Peng, Lun Zhao, Wei-Hua Tong
  • Patent number: 9543098
    Abstract: A relay and a method for indicating a relay failure may be provided, whereby the relay comprises a switch assembly capable of providing a trigger signal based on a switching status; an energisation element capable of energisation to affect the switch assembly; and a light indication for indicating a switching status of the switch assembly.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: January 10, 2017
    Assignee: SCHNEIDER ELECTRIC INDUSTRIES SAS
    Inventors: Sachin Sakharam Chopade, Yong Meng Wah, Ya Chee Yeong
  • Patent number: 9524911
    Abstract: Methods for creating self-aligned FINFET SDBs for minimum gate junction pitch and epitaxy formation. Embodiments include forming separated openings in a hard mask on upper surfaces of Si fins; forming cavities in the fins, each of the cavities having a concave shape and a width extending under the hard mask on each side of the cavity; forming trenches in the fins, the trenches having an upper width substantially equal to a width of the openings and less than the width of a cavity; removing the hard mask; filling the trenches and the cavities with oxide, forming STI regions; forming an oxide mask layer on the upper surfaces of the fins and the STI regions; removing upper portions of the oxide in sections between the STI regions; and removing remaining portions of the oxide mask revealing the fins and upper surfaces of the STI regions.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hao-Cheng Tsai, Yong Meng Lee, Min-hwa Chi
  • Publication number: 20160163702
    Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed.
    Type: Application
    Filed: December 4, 2014
    Publication date: June 9, 2016
    Inventors: Xusheng WU, Yue HU, Xin WANG, Yong Meng LEE, Wen-Pin PENG, Lun ZHAO, Wei-Hua TONG
  • Publication number: 20160049488
    Abstract: A semiconductor structure with wide-bottom and/or wide-top gates includes a semiconductor substrate, a source region(s), a drain region(s) associated with the source region(s), and a gate(s) associated with the source region(s) and the drain region(s) having a top portion and a bottom portion. One of the top portion and the bottom portion of the gate(s) is wider than the other of the top portion and bottom portion. The wide-bottom gate is created using a dummy wide-bottom gate etched from a layer of dummy gate material, creating spacers for the dummy gate, removing the dummy gate material and filling the opening created with conductive material. For the wide-top gate, first and second spacers are included, and instead of removing all the dummy gate material, only a portion is removed, exposing the first spacers. The exposed portion of the first spacers may either be completely or partially removed (e.g., tapered), in order to increase the area of the top portion of the gate to be filled.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Yan Ping SHEN, Haiting WANG, Min-hwa CHI, Yong Meng LEE
  • Patent number: 9209258
    Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Feng Zhou, Tien-Ying Luo, Haiting Wang, Padmaja Nagaiah, Jean-Baptiste Laloe, Isabelle Pauline Ferain, Yong Meng Lee
  • Patent number: 9202697
    Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: December 1, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tien-Ying Luo, Feng Zhou, Yan Ping Shen, Haiting Wang, Haoran Shi, Wei Hua Tong, Seung Kim, Yong Meng Lee
  • Patent number: 9147572
    Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ashish Kumar Jha, Haiting Wang, Meng Luo, Yong Meng Lee
  • Publication number: 20150249136
    Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 3, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Feng ZHOU, Tien-Ying LUO, Haiting WANG, Padmaja NAGAIAH, Jean-Baptiste LALOE, Isabelle Pauline FERAIN, Yong Meng LEE
  • Patent number: 9123783
    Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: September 1, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xin Wang, Changyong Xiao, Yue Hu, Yong Meng Lee, Meng Luo, Jialin Weng, Wei Hua Tong, Wen-Pin Peng
  • Publication number: 20150024585
    Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Tien-Ying LUO, Feng ZHOU, Yan Ping SHEN, Haiting WANG, Haoran SHI, Wei Hua TONG, Seung KIM, Yong Meng LEE
  • Publication number: 20140339612
    Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 20, 2014
    Applicant: GlobalFoundries Inc.
    Inventors: Ashish Kumar JHA, Haiting WANG, Meng LUO, Yong Meng LEE
  • Publication number: 20140175562
    Abstract: A semiconductor structure in fabrication includes a NFET and a PFET. Spacers adjacent gate structures of the NFET and PFET have undesired divots that can lead to substrate damage from chemicals used in a subsequent etch. The fabrication also leaves hard masks over the gate structures with non-uniform height. The divots are filled with material resistant to the chemicals used in the etch. Excess filler is removed, and uniform height is restored. Further fabrication may then proceed.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Haiting Wang, Huang Liu, Yong Meng Lee, Songkram Srivathanakul
  • Publication number: 20140151760
    Abstract: A method of filling gaps between gates with doped flowable pre-metal dielectric (PMD) and the resulting device are disclosed. Embodiments include forming at least two dummy gates on a substrate, each dummy gate being surrounded by spacers; filling a gap between adjacent spacers of the at least two dummy gates with a flowable PMD; implanting a dopant in the flowable PMD; and annealing the flowable PMD. Doping the flowable PMD prevents erosion of the PMD, thereby providing a voidless gap-fill.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 5, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Haiting WANG, Po-Wen CHAN, Yan Ping SHEN, Yong Meng LEE
  • Publication number: 20140131881
    Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xin Wang, Changyong Xiao, Yue Hu, Yong Meng Lee, Meng Luo, Jialin Weng, Wei Hua Tong, Wen-Pin Peng
  • Patent number: 8716081
    Abstract: A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: May 6, 2014
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Shailendra Mishra, Johnny Widodo