Patents by Inventor Yong-Min Kwon

Yong-Min Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150228867
    Abstract: A light emitting diode package includes a package body having first and second electrode structures, a light emitting diode chip having a surface, on which first and second electrodes are disposed. The light emitting diode chip is disposed on the first and second electrode structures of the package body. A sheet-type wavelength conversion layer having a substantially constant thickness is disposed on an upper surface of the light emitting diode chip, and an encapsulating portion is disposed to surround the light emitting diode chip and the wavelength conversion layer. The encapsulating portion has an upper surface substantially parallel to the wavelength conversion layer. Side surfaces of the encapsulating portion have a plurality of side slope sections inclined toward the upper surface of the encapsulating portion.
    Type: Application
    Filed: November 14, 2014
    Publication date: August 13, 2015
    Inventors: Jung Jin KIM, Yong Min KWON, Min Young SON, Sung Kyong OH
  • Patent number: 9059149
    Abstract: The present application provides an electronic device package. The package includes a packaging substrate having first and second surfaces opposing one another. First and second electrode patterns are formed on the first surface and first and second external terminals connected to the first and second electrode patterns. The second electrode pattern is electrically insulated from the first electrode pattern and surrounds the first electrode pattern An electronic device is mounted on the first surface of the packaging substrate and includes first and second electrodes disposed on a surface thereof facing the packaging substrate. The first and second electrodes are positioned on the first and second electrode patterns, respectively.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: June 16, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Min Kwon, Seo Hyun Moon, Sung Jun Im, Min Young Son
  • Publication number: 20140377894
    Abstract: A method of manufacturing a semiconductor light emitting device package includes providing a wafer and forming, on the wafer, a semiconductor laminate comprising a plurality of light emitting devices. Electrodes are formed in respective light emitting device regions of the semiconductor laminate. A curable resin is applied to a surface of the semiconductor laminate on which the electrodes are formed. A support structure is formed for supporting the semiconductor laminate by curing the curable resin. Through holes are formed in the support structure to expose the electrodes therethrough. Connection electrodes are formed in the support structure to be connected to the exposed electrodes.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 25, 2014
    Inventors: Yong Min KWON, Jung Jin KIM, Hak Hwan KIM, Sung Jun IM
  • Publication number: 20140339581
    Abstract: A semiconductor light emitting device package is provided having a light transmissive substrate, and a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially laminated on the light transmissive substrate. The light emitting structure comprises a first surface and a second opposing surface facing the light transmissive substrate. The semiconductor light emitting device package comprises a via penetrating the second conductivity-type semiconductor layer and the active layer, and exposing the first conductivity-type semiconductor layer. A first electrode has a first portion disposed on the first surface, and a second portion extending into the via and contacting the first conductivity-type semiconductor layer. An insulating layer is disposed between the first electrode, and each of the second conductivity type semiconductor layer, the active layer, and the first surface.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 20, 2014
    Inventors: Yong Min KWON, Hak Hwan KIM, Min Young SON, Sung Jun IM
  • Publication number: 20140306261
    Abstract: There is provided an electronic device package including an electronic device including a first electrode and a second electrode disposed on a surface thereof, a package substrate having a first surface having the electronic device mounted thereon and a second surface opposed to the first surface. The package substrate includes a first electrode pattern and a second electrode pattern electrically connected to the first electrode and the second electrode on the first surface, respectively. The package substrate further includes at least one via hole disposed outside of a region for mounting the electronic device and an irregular portion disposed on the first surface to be adjacent to the via hole.
    Type: Application
    Filed: April 11, 2014
    Publication date: October 16, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Jun IM, Min Young SON, Yong Min KWON, Hak Hwan KIM
  • Publication number: 20140246648
    Abstract: A light emitting device package, comprises a light emitting structure having first and second electrodes insulated from each other; and a support structure. The support structure comprises: a first support electrode electrically connected to the first electrode of the light emitting structure; a second support electrode electrically connected to the second electrode of the light emitting structure, the second support electrode spaced apart from, and electrically insulated from, the first support electrode; and a support connection portion between the first support electrode and the second support electrode. The light emitting structure includes a protrusion portion that protrudes in a horizontal direction beyond a sidewall of at least one of the first support electrode and the second support electrode so that a void is present below the protrusion portion and above a plane extending from bottoms of the first and second support electrodes.
    Type: Application
    Filed: February 21, 2014
    Publication date: September 4, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung Jun Im, Dong Hyun Cho, Jong Rak Sohn, Yong Min Kwon
  • Publication number: 20140203451
    Abstract: The present application provides an electronic device package. The package includes a packaging substrate having first and second surfaces opposing one another. First and second electrode patterns are formed on the first surface and first and second external terminals connected to the first and second electrode patterns. The second electrode pattern is electrically insulated from the first electrode pattern and surrounds the first electrode pattern An electronic device is mounted on the first surface of the packaging substrate and includes first and second electrodes disposed on a surface thereof facing the packaging substrate. The first and second electrodes are positioned on the first and second electrode patterns, respectively.
    Type: Application
    Filed: October 25, 2013
    Publication date: July 24, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Min KWON, Seo Hyun MOON, Sung Jun IM, Min Young SON
  • Patent number: 7446384
    Abstract: The present invention relates to an image sensor module and a manufacturing method thereof, especially to a wafer level chip size package (WL-CSP) realized by directly contacting an image sensor chip wafer to a glass wafer on which an IR filter coating layer is deposited, an electrode rearrangement and a dicing process, a miniaturized image sensor module using this wafer level chip size package (WL-CSP) and a method thereof. The CMOS image sensor module using a wafer level chip size package technology according to the present invention comprises: an image sensor chip wafer having a partition with a lattice structure formed at portions except an image sensing area; and a glass wafer with an IR filter coating layer and a metal electrode; and wherein the image sensor chip wafer and the glass wafer form an electric contact and a chip sealing by a flip-chip bonding; and wherein a solder bump and a non solder bump are formed after a metal wiring is rearranged on a lower surface of the glass wafer.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: November 4, 2008
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Kyung-Wook Paik, Myung-Jin Yim, Ho-Young Son, Yong-Min Kwon
  • Publication number: 20060252246
    Abstract: The present invention relates to an image sensor module and a manufacturing method thereof, especially to a wafer level chip size package (WL-CSP) realized by directly contacting an image sensor chip wafer to a glass wafer on which an IR filter coating layer is deposited, an electrode rearrangement and a dicing process, a miniaturized image sensor module using this wafer level chip size package (WL-CSP) and a method thereof. The CMOS image sensor module using a wafer level chip size package technology according to the present invention comprises: an image sensor chip wafer having a partition with a lattice structure formed at portions except an image sensing area; and a glass wafer with an IR filter coating layer and a metal electrode; and wherein the image sensor chip wafer and the glass wafer form an electric contact and a chip sealing by a flip-chip bonding; and wherein a solder bump and a non solder bump are formed after a metal wiring is rearranged on a lower surface of the glass wafer.
    Type: Application
    Filed: April 3, 2006
    Publication date: November 9, 2006
    Inventors: Kyung-Wook Paik, Myung-Jin Yim, Ho-Young Son, Yong-Min Kwon