Abstract: The present invention relates to new BARD1 isoforms specific to lung cancer and colorectal cancer, a method for detecting thereof and a method for treating and/or preventing lung cancer and colorectal cancer.

Abstract: A machine for testing the parts and functions of a mobile phone includes a supporting mechanism, a platform, a receiving portion, and a detecting mechanism. The supporting mechanism is mounted in a box. The platform is slidably mounted on the supporting mechanism. The receiving portion is used to receive the mobile phone. The receiving portion is rotatably mounted on the platform. Devices within the machine are operated to test the mobile phone. A mobile phone testing system used in the testing machine is also described.

Abstract: The present invention relates to new BARD1 isoforms specific to lung cancer and colorectal cancer, a method for detecting thereof and a method for treating and/or preventing lung cancer and colorectal cancer.

Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

Abstract: The present invention relates to improved semi-automated methods that permit the extraction of nucleic acids from samples, preparation of PCR and post-PCR preparation steps of DNA-libraries for next-generation sequencings methods that can be conducted. The methods and additional aspects relating to such methods are less laborious, safe costs, reagents and are less prone to contamination than comparable methods that are not automated.

Abstract: An embodiment includes an apparatus with a housing wearable by a subject and a first sensor operable to detect a position of the subject. An embodiment of the apparatus includes a second sensor operable to detect a body state of the subject, where the first body state may be a vital sign such as heart rate, blood pressure, body temperature or respiratory rate. The apparatus may also include a wireless module, and be operable to transmit body state data and position data to a remote device. The apparatus may include a gyroscope or an accelerometer, and may be operable to detect rotational change in the subject's position about an axis, linear acceleration of the subject along an axis, a change in position of the subject, or a rate of change in position of the subject.

Abstract: An embodiment comprises and apparatus having an image capture device with an image axis and a gyroscope operable to indicate the orientation of the image axis. An embodiment of a capsule endoscopy system comprises an imaging capsule and an external unit. The imaging capsule may comprise an image capture device having an image axis and a gyroscope operable to indicate the orientation of the image axis. The external unit may comprise a gyroscope operable to indicate an orientation of a subject and a harness wearable by a subject and operable to align the gyroscope with the subject. The imaging capsule may send and image to an external unit for processing and display, and the external unit may provide for calculation of the image-axis orientation relative to the body.

Abstract: Some microprocessors check branch prediction information in a branch history table and/or a branch target buffer. To check for branch prediction information, a microprocessor can identify which instructions are control flow instructions and which instructions are non control flow instructions. To reduce power consumption in the branch history table and/or branch target buffer, the branch history table and/or branch target buffer can check for branch prediction information corresponding to the control flow instructions and not the non control flow instructions.

Abstract: Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.

Abstract: A centrifugal impeller includes a cover, a base opposite the cover and a plurality of blades. The cover has an inlet. The plurality of blades surround the inlet and are arranged between and connect the cover and the base. Inlet edges of one end of the blades adjacent the center of the impeller define a cavity in communicate with the inlet. The dimension of the cavity gradually decreases along the direction from the cover towards the base.

Abstract: A control device and a control method during bypassing of power units are provided. The method includes: detecting a first three-phase output electrical signal; calculating a first positive sequence component and a first negative sequence component of the first three-phase output electrical signal; providing a given positive sequence component and a given negative sequence component so as to respectively perform the closed-loop compensation on the first positive sequence component and the first negative sequence component, thereby outputting a second positive sequence component and a second negative sequence component; superimposing the second positive sequence component and the second negative sequence component; and outputting a second three-phase output electrical signal in a preset way.

Abstract: A power module, which is connected to a power source, includes a rectifying unit, a filtering unit and an inverter. The rectifying unit has three legs. The filtering unit is connected to the rectifying unit, and the inverter is connected to the filtering unit. One of the three legs has two switching elements connected in series, and another one of the three legs has two rectifying elements connected in series. In addition, a power conversion apparatus including the power module is also disclosed.

Abstract: A method for programming extended display identification data (EDID) adapted to a display device is provided. The display device has at least one EDID chip, a microcontroller unit chip, and a flash memory chip. in the method, a first EDID corresponding to the EDID chip is written into a firmware stored in the flash memory chip. The display device is powered on. The first EDID in the firmware is automatically written into the corresponding EDID chip as a second EDID by the microcontroller unit chip.

Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

Abstract: A control device and a control method during bypassing of power units are provided. The method includes: detecting a first three-phase output electrical signal; calculating a first positive sequence component and a first negative sequence component of the first three-phase output electrical signal; providing a given positive sequence component and a given negative sequence component so as to respectively perform the closed-loop compensation on the first positive sequence component and the first negative sequence component, thereby outputting a second positive sequence component and a second negative sequence component; superimposing the second positive sequence component and the second negative sequence component; and outputting a second three-phase output electrical signal in a preset way.

Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

Abstract: A motor has a stator and a rotor. The stator has 2P poles wherein P is an integer greater than one. The rotor has a shaft, a rotor core and a commutator fixed to the shaft. The commutator has m segments where m is an even integer greater than P. Every two adjacent segments are electrically connected by a winding unit so that the rotor winding comprises m winding units with at least one of the winding units comprising P coils connected in series; and each coil of each winding unit is directly connected to a corresponding two segments.

Abstract: A power module, which is connected to a power source, includes a rectifying unit, a filtering unit and an inverter. The rectifying unit has three legs. The filtering unit is connected to the rectifying unit, and the inverter is connected to the filtering unit. One of the three legs has two switching elements connected in series, and another one of the three legs has two rectifying elements connected in series. In addition, a power conversion apparatus including the power module is also disclosed.

Abstract: A technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. In an embodiment, each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

Abstract: The present invention relates to new BARD1 isoforms specific to lung cancer and colorectal cancer, a method for detecting thereof and a method for treating and/or preventing lung cancer and colorectal cancer.