Abstract: A shading panel is described for shading light emitting elements of a light emitting diode display system. The shading panel defines a substantially plane panel surface having an upper border and a lower border, the shading panel comprising at least one column of at least two openings aligned according to a column direction, each opening being suitable to receive at least one light emitting element. For each pair of adjacent openings of the at least one column of openings, the shading panel comprises a first shading louver and a second shading louver, the first shading louver being positioned closer to the opening of the pair of openings closest to the upper border, the second shading louver being positioned closer to the opening of the pair of openings closest to the lower border. The height of the first shading louver is smaller than the height of the second shading louver.

Abstract: A system for recovering an architecture register mapping table (ARMT). The system includes a first number of collection circuits and decode circuits, a second number of selection circuits, and an enable circuit. Information related to the mapping between each physical register and an appropriate architecture register is obtained from a physical register mapping table (PRMT) by one and only one collection circuit during only one of a fourth number of instruction cycles. Each decode circuit has its input coupled to the output of one different collection circuit and is capable of converting its input into a third number bit wide binary string selection code at its output. Each selection circuit is configured to receive from each selection code a bit from a bit position associated with that selection circuit. The enable circuit is configured to appropriately enable mapping of information from the PRMT to the ARMT.

Abstract: Apparatus for driving a nozzle of a bidet toilet, has a base 1; a nozzle 2; a guide device 11, 12 formed on the base for guiding linear movement of the nozzle; a motion output device 7 having an output shaft 71; a driving wheel 3 attached to the output shaft and being rotatably driven with the output shaft; a pair of guide wheels 4,5 rotatably fixed relative to the base, and a non-toothed conveyer 6 wound around the driving wheel 3 and the guide wheels 4, 5 and fastened to the nozzle 2. Rotation of the driving wheel 3 causes linear movement of the nozzle 2.

Abstract: A comparison circuit can reduce the amount of power consumed when searching a load queue or a store queue of a microprocessor. Some embodiments of the comparison circuit use a comparison unit that performs an initial comparison of addresses using a subset of the address bits. If the initial comparison results in a match, a second comparison unit can be enabled to compare another subset of the address bits.

Abstract: An embodiment comprises includes an apparatus with a housing wearable by a subject and a first sensor operable to detect a position of the subject. An embodiment of the apparatus includes a second sensor operable to detect a body state of the subject, where the first body state may be a vital sign such as heart rate, blood pressure, body temperature or respiratory rate. The apparatus may also include a wireless module, and be operable to transmit body state data and position data to a remote device. The apparatus may include a gyroscope or an accelerometer, and may be operable to detect rotational change in the subject's position about and axis, linear acceleration of the subject along an axis, a change in position of the subject, or a rate of change in position of the subject.

Abstract: In a network-on-chip (NoC) system, multiple data messages may be transferred among modules of the system. Power consumption due to the transfer of the messages may affect a cost and overall performance of the system. A described technique provides a way to reduce a volume of data transferred in the NoC system by exploiting redundancy of data messages. Thus, if a data message to be sent from a source in the NoC includes so-called “zero” bytes that are bytes including only bits set to “0,” such zero bytes may not be transmitted in the NoC. Information on whether each byte of the data message is a zero byte may be recorded in a storage such as a data structure. This information, together with non-zero bytes of the data message, may form a compressed version of the data message. The information may then be used to uncompress the compressed data message at a destination.

Abstract: An embodiment of an instruction pipeline includes first and second sections. The first section is operable to provide first and second ordered instructions, and the second section is operable, in response to the second instruction, to read first data from a data-storage location, is operable, in response to the first instruction, to write second data to the data-storage location after reading the first data, and is operable, in response to the writing the second data after reading the first data, to cause the flushing of a some, but not all, of the pipeline. Such an instruction pipeline may reduce the processing time lost and the energy expended due to a pipeline flush by flushing only a portion of the pipeline instead of flushing the entire pipeline.

Abstract: An embodiment comprises and apparatus having an image capture device with an image axis and a gyroscope operable to indicate the orientation of the image axis. An embodiment of a capsule endoscopy system comprises an imaging capsule and an external unit. The imaging capsule may comprise an image capture device having an image axis and a gyroscope operable to indicate the orientation of the image axis. The external unit may comprise a gyroscope operable to indicate an orientation of a subject and a harness wearable by a subject and operable to align the gyroscope with the subject. The imaging capsule may send and image to an external unit for processing and display, and the external unit may provide for calculation of the image-axis orientation relative to the body.

Abstract: A shading panel is described for shading light emitting elements of a light emitting diode display system. The shading panel defines a substantially plane panel surface having an upper border and a lower border, the shading panel comprising at least one column of at least two openings aligned according to a column direction, each opening being suitable to receive at least one light emitting element. For each pair of adjacent openings of the at least one column of openings, the shading panel comprises a first shading louver and a second shading louver, the first shading louver being positioned closer to the opening of the pair of openings closest to the upper border, the second shading louver being positioned closer to the opening of the pair of openings closest to the lower border. The height of the first shading louver is smaller than the height of the second shading louver.

Abstract: A motor comprises a stator and a rotor. The stator comprises 2P poles wherein P is an integer greater than one. The rotor comprises a shaft, a rotor core and a commutator fixed to the shaft. The commutator comprises m segments where m is an even integer greater than P. Every two adjacent segments are electrically connected by a winding unit so that the rotor winding comprises m winding units with at least one of the winding units comprising P coils connected in series; and each coil of each winding unit is directly connected to a corresponding two segments.

Abstract: A shift-by-wire shifter system includes a spring biased DTP lever engageable with a shifter lever assembly to move the shifter lever assembly to a park position. A DTP lock assembly secures the DTP lever so that the shifter lever assembly is selectively movable along the shift path during normal operation and releases the DTP lever so that the DTP lever moves the shifter lever assembly to the park position upon the loss of system power. A DTP actuator unlocks the shifter lever assembly and the DPT lock assembly upon the loss of system power so that the DTP lever automatically moves the shifter lever assembly to the park position upon the loss of system power. A power storage device is provided to release power to the DPT actuator upon the loss of system power.

Abstract: Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.

Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

Abstract: A system for recovering an architecture register mapping table (ARMT). The system includes a first number of collection circuits and decode circuits, a second number of selection circuits, and an enable circuit. Information related to the mapping between each physical register and an appropriate architecture register is obtained from a physical register mapping table (PRMT) by one and only one collection circuit during only one of a fourth number of instruction cycles. Each decode circuit has its input coupled to the output of one different collection circuit and is capable of converting its input into a third number bit wide binary string selection code at its output. Each selection circuit is configured to receive from each selection code a bit from a bit position associated with that selection circuit. The enable circuit is configured to appropriately enable mapping of information from the PRMT to the ARMT.

Abstract: An embodiment of a technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. Each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

Abstract: Some microprocessors check branch prediction information in a branch history table and/or a branch target buffer. To check for branch prediction information, a microprocessor can identify which instructions are control flow instructions and which instructions are non control flow instructions. To reduce power consumption in the branch history table and/or branch target buffer, the branch history table and/or branch target buffer can check for branch prediction information corresponding to the control flow instructions and not the non control flow instructions.

Abstract: A comparison circuit can reduce the amount of power consumed when searching a load queue or a store queue of a microprocessor. Some embodiments of the comparison circuit use a comparison unit that performs an initial comparison of addresses using a subset of the address bits. If the initial comparison results in a match, a second comparison unit can be enabled to compare another subset of the address bits.

Abstract: The present invention is to provide a lithium battery can be exempted from short circuit problems caused by metallic particles agitated through the manufacturing process and later usage. Said lithium battery includes a battery cover, anode films, separators, cathode films, an organic electrolyte, a cylindrical housing with a neck portion formed on an upper portion of the cylindrical housing. Said neck portion is spread with a layer of polymeric based composite materials onto an inner wall inside the neck portion, damages happened to the neck portion will not cause short circuit also.

Abstract: Apparatus for driving a nozzle of a bidet toilet, has a base 1; a nozzle 2; a guide device 11, 12 formed on the base for guiding linear movement of the nozzle; a motion output device 7 having an output shaft 71; a driving wheel 3 attached to the output shaft and being rotatably driven with the output shaft; a pair of guide wheels 4,5 rotatably fixed relative to the base, and a non-toothed conveyer 6 wound around the driving wheel 3 and the guide wheels 4, 5 and fastened to the nozzle 2. Rotation of the driving wheel 3 causes linear movement of the nozzle 2.

Abstract: A shifter lever assembly includes a base, a shifter lever movable relative to the base along a shift path, and at least one gate defining a gear position along the shift path. A release mechanism includes a gate pin movable along a linear path between a locked position wherein the gate pin cooperates with the at least one gate to secure the shifter lever in the gear position and an unlocked position wherein the shifter lever is movable from the gear position along the shift path, an actuator operatively coupled to the gate pin to selectively move the gate pin from the locked position to the unlocked position, and at least one rotatable roller located between the gate pin and the at least one gate.