Abstract: An embodiment solid electrolyte includes a first compound and a second compound. The first compound is represented by a first chemical formula Li7-aPS6-a(X11-bX2b)a, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, and wherein 0<a?2 and 0<b<1, and the second compound is represented by a second chemical formula Li7-cP1-2dMdS6-c-3d(X11-eX2e)c, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, wherein M represents Ge, Si, Sn, or any combination thereof, and wherein 0<c?2, 0<d<0.5, and 0<e<1.

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

Abstract: An apparatus for manufacturing a secondary battery includes: an index table configured to receive a secondary battery cell, the secondary battery cell including an electrode assembly, a can accommodating the electrode assembly, and an electrode tab between the electrode assembly and the can to electrically connect the electrode assembly to the can; a laser scanner configured to irradiate laser onto an outer surface of the can to weld the electrode tab to the can; and a controller configured to variably control the laser scanner according to an operation of the index table.

Abstract: A display device and method for manufacturing thereof are provided. The display device includes a substrate having a display area and a non-display area, and including an edge, an upper surface having an edge area in which a processing trace remains adjacent to the edge, a bottom surface opposite to the upper surface, a side surface connected to the upper surface and not parallel thereto, and a first inclined surface connected to the side surface and to the bottom surface, a light-emitting element layer above the upper surface of the substrate in the display area, and including light-emitting elements, an encapsulating layer above the light-emitting element layer and corresponding to a portion of the display area and the non-display area, and a protective layer above an outer surface of the substrate, and located on at least one of the bottom surface, the side surface, or the first inclined surface.

Abstract: A seat for a vehicle, includes a second row center seat and a second row side seat provided on a partition wall positioned rearward of a driver seat, the second row center seat may move leftward or rightward, and an interval between the seats may be increased in a state in which the second row center seat is moved in a right direction away from the second row side seat, which makes it possible to maximally prevent body contact between a passenger in the second row center seat and a passenger in the second row side seat.

Abstract: A display device includes: a substrate including a display area and a non-display area surrounding the display area; a light emitting element layer on the display area on the substrate and including a plurality of light emitting elements; and an encapsulating layer on the light emitting element layer and on a portion of the display area and the non-display area; and wherein the substrate comprises an upper surface on which the light emitting element layer is located, a bottom surface opposite to the upper surface, a side surface connected to the upper surface and not parallel to the upper surface, and a first inclined surface connected to the side surface and the bottom surface and not parallel to the side surface and the bottom surface, wherein an edge area of the upper surface of the substrate adjacent to an edge of the substrate, in which a processing trace remains.

Abstract: An activation function processing method includes processing a first activation function in a first mode by referring to a shared lookup table that includes a plurality of function values of the first activation function; and processing a second activation function in a second mode by referring to the shared lookup table, the second activation function being a different function than the first activation function.

Abstract: A display device includes: a substrate comprising an upper surface, a bottom surface facing the upper surface, and a through hole penetrating the upper surface and the bottom surface; and a light emitting element layer on the upper surface of the substrate, wherein the substrate comprises a side surface that meets the upper surface in the through hole, a first surface that meets the bottom surface, a second surface that meets the side surface, and a third surface between the first surface and the second surface, and wherein the first surface and the second surface are spaced apart from each other with the third surface therebetween, and are inclined surfaces.

Abstract: The present disclosure relates to a vehicle rear seat including: a center seat; and side seats located on the left and right of the center seat, wherein, the center seat is capable of protruding by moving the center seat forward with respect to the side seats, and in the state in which the center seat protrudes forward, it is possible to increase an inter-passenger distance so that physical contact between the passenger of the center seat and the passenger of each of the side seats can be prevented as much as possible.

Abstract: An electronic device includes a display device, which may be fabricated using a described method. The display device includes a glass substrate including a first surface, a second surface opposite the first surface, and a side surface between the first surface and the second surface, an outermost structure on the first surface of the glass substrate and located adjacent to an edge of one side of the glass substrate, and a display area including a plurality of light emitting areas on the first surface of the glass substrate and located farther from the edge of the one side of the glass substrate than the outermost structure is. A minimum distance from the side surface of the glass substrate to the outermost structure is equal to 130 ?m or less.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

Abstract: A data bus inversion (DBI) circuit of a memory device includes a first processing component configured to generate first combination data by combining read data read from a memory cell region and previous data previously outputted from a data line, and generate second combination data by selectively inverting the first combination data depending on a result of comparing the first combination data and the previous data; and a second processing component configured to generate data to be outputted from the data line, by combining the second combination data and the previous data, wherein the second processing component generates bits of unnecessary bit positions in the data to be the same as bits of the unnecessary bit positions in the previous data.

Abstract: A semiconductor device includes a base substrate comprising a first region and a second region, a photonics device disposed in the first region, the photonics device comprising a first doped layer disposed on the base substrate, and a second doped layer disposed on the first doped layer so that at least a portion vertically overlaps the first doped layer, the second doped layer having a first vertical thickness, and a transistor disposed in the second region, the transistor comprising a semiconductor layer disposed on the base substrate and horizontally spaced apart from the first doped layer, and a gate electrode horizontally spaced apart from the second doped layer and disposed on the semiconductor layer, disposed at the same vertical level as that of the second doped layer, and having a second vertical thickness equal to the first vertical thickness.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

Abstract: A data processing system includes a host and an accelerator. The host transmits, to the accelerator, input data together with data identification information based on a data classification criterion. The accelerator classifies the input data as any one of feature data, a parameter, and a bias based on the data identification information when the input data is received from the host, distributes the input data, performs pre-processing on the feature data, and outputs computed result data to the host or feeds the result data back so that computation processing is performed on the result data again.

Abstract: A data bus inversion (DBI) circuit of a memory device includes a first processing component configured to generate first combination data by combining read data read from a memory cell region and previous data previously outputted from a data line, and generate second combination data by selectively inverting the first combination data depending on a result of comparing the first combination data and the previous data; and a second processing component configured to generate data to be outputted from the data line, by combining the second combination data and the previous data, wherein the second processing component generates bits of unnecessary bit positions in the data to be the same as bits of the unnecessary bit positions in the previous data.

Abstract: An image sensor includes a substrate having an element separation pattern, a first active region, and a ground region, the ground region being separated from the first active region by the element separation pattern, a transfer transistor including a transfer gate electrode on the first active region, the transfer gate electrode being separated from the ground region by the element separation pattern, a photo diode within the substrate, the photo diode being spaced apart from the transfer gate electrode, and a contact on the ground region, the contact being configured to receive a ground voltage.

Abstract: A computation circuit includes a plurality of processing elements and a common accumulator. The plurality of processing elements are sequentially coupled in series, and performs a multiply and accumulate (MAC) operation on a weight signal and at least one of two or more input signals received in each unit cycle. The common accumulator is sequentially and cyclically coupled to first to Kth processing elements among the plurality of processing elements, and configured to receive a computation value outputted from a processing element coupled thereto among the first to Kth processing elements, and store computation information. The K is decided based on values of the two or more input signals and the number of guard bits included in one processing element.

Abstract: A computation device includes a buffer memory which provides first to b input feature sets to the computation unit. The buffer memory includes first to nth memories, and configured to divide and store the first to nth input feature sets each including a plurality of features in the first to nth memories, respectively. The plurality of features of one input feature set is divided and stored into the first to nth memories. Features having the same turn in the first to nth input feature sets are stored one by one in the first to nth memories.