Abstract: An activation function processing method includes processing a first activation function in a first mode by referring to a shared lookup table that includes a plurality of function values of the first activation function; and processing a second activation function in a second mode by referring to the shared lookup table, the second activation function being a different function than the first activation function.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

Abstract: A data bus inversion (DBI) circuit of a memory device includes a first processing component configured to generate first combination data by combining read data read from a memory cell region and previous data previously outputted from a data line, and generate second combination data by selectively inverting the first combination data depending on a result of comparing the first combination data and the previous data; and a second processing component configured to generate data to be outputted from the data line, by combining the second combination data and the previous data, wherein the second processing component generates bits of unnecessary bit positions in the data to be the same as bits of the unnecessary bit positions in the previous data.

Abstract: A semiconductor device includes a base substrate comprising a first region and a second region, a photonics device disposed in the first region, the photonics device comprising a first doped layer disposed on the base substrate, and a second doped layer disposed on the first doped layer so that at least a portion vertically overlaps the first doped layer, the second doped layer having a first vertical thickness, and a transistor disposed in the second region, the transistor comprising a semiconductor layer disposed on the base substrate and horizontally spaced apart from the first doped layer, and a gate electrode horizontally spaced apart from the second doped layer and disposed on the semiconductor layer, disposed at the same vertical level as that of the second doped layer, and having a second vertical thickness equal to the first vertical thickness.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

Abstract: A data processing system includes a host and an accelerator. The host transmits, to the accelerator, input data together with data identification information based on a data classification criterion. The accelerator classifies the input data as any one of feature data, a parameter, and a bias based on the data identification information when the input data is received from the host, distributes the input data, performs pre-processing on the feature data, and outputs computed result data to the host or feeds the result data back so that computation processing is performed on the result data again.

Abstract: A data bus inversion (DBI) circuit of a memory device includes a first processing component configured to generate first combination data by combining read data read from a memory cell region and previous data previously outputted from a data line, and generate second combination data by selectively inverting the first combination data depending on a result of comparing the first combination data and the previous data; and a second processing component configured to generate data to be outputted from the data line, by combining the second combination data and the previous data, wherein the second processing component generates bits of unnecessary bit positions in the data to be the same as bits of the unnecessary bit positions in the previous data.

Abstract: An image sensor includes a substrate having an element separation pattern, a first active region, and a ground region, the ground region being separated from the first active region by the element separation pattern, a transfer transistor including a transfer gate electrode on the first active region, the transfer gate electrode being separated from the ground region by the element separation pattern, a photo diode within the substrate, the photo diode being spaced apart from the transfer gate electrode, and a contact on the ground region, the contact being configured to receive a ground voltage.

Abstract: A computation circuit includes a plurality of processing elements and a common accumulator. The plurality of processing elements are sequentially coupled in series, and performs a multiply and accumulate (MAC) operation on a weight signal and at least one of two or more input signals received in each unit cycle. The common accumulator is sequentially and cyclically coupled to first to Kth processing elements among the plurality of processing elements, and configured to receive a computation value outputted from a processing element coupled thereto among the first to Kth processing elements, and store computation information. The K is decided based on values of the two or more input signals and the number of guard bits included in one processing element.

Abstract: A computation device includes a buffer memory which provides first to b input feature sets to the computation unit. The buffer memory includes first to nth memories, and configured to divide and store the first to nth input feature sets each including a plurality of features in the first to nth memories, respectively. The plurality of features of one input feature set is divided and stored into the first to nth memories. Features having the same turn in the first to nth input feature sets are stored one by one in the first to nth memories.

Abstract: An activation function processing method includes processing a first activation function in a first mode by referring to a shared lookup table that includes a plurality of function values of the first activation function; and processing a second activation function in a second mode by referring to the shared lookup table, the second activation function being a different function than the first activation function.

Abstract: A neural network computation apparatus includes a first processing block including a plurality of processing units that each perform a matrix multiplication operation on input data and weights, and a second processing block including a plurality of element-wise operation processing groups. The element-wise operation processing group selectively perform a first neural network computation operation and a second neural network computation operation. The first neural network computation operation comprises the matrix multiplication operation on the input data and the weights and an activation operation on a result value of the matrix multiplication operation, and the second neural network computation operation comprises an activation operation on the result value of the matrix multiplication operation, which is transferred from the first processing block, and an element-wise operation.

Abstract: A memory controller includes a temperature monitor configured to update temperature states of a memory device divided into groups as temperature scores and a scheduler configured to update a command score using the temperature scores and change a priority of the command score to match with a current operation mode.

Abstract: A data processing system includes a host and an accelerator. The host transmits, to the accelerator, input data together with data identification information based on a data classification criterion. The accelerator classifies the input data as any one of feature data, a parameter, and a bias based on the data identification information when the input data is received from the host, distributes the input data, performs pre-processing on the feature data, and outputs computed result data to the host or feeds the result data back so that computation processing is performed on the result data again.

Abstract: A computation device includes a buffer memory which provides first to b input feature sets to the computation unit. The buffer memory includes first to nth memories, and configured to divide and store the first to nth input feature sets each including a plurality of features in the first to nth memories, respectively. The plurality of features of one input feature set is divided and stored into the first to nth memories. Features having the same turn in the first to nth input feature sets are stored one by one in the first to nth memories.

Abstract: There are provided a memory controller and a memory system having the same. The memory controller is included in the memory system for storing data and transmits data between the memory system and a host system. The memory controller includes: a buffer including a plurality of blocks for storing the data, the buffer inputting or outputting the data through a first bus having a first data width or a second bus having a second data width; and a data width controller for mapping the blocks according to the first and second data widths.

Abstract: A memory controller includes a temperature monitor configured to update temperature states of a memory device divided into groups as temperature scores and a scheduler configured to update a command score using the temperature scores and change a priority of the command score to match with a current operation mode.

Abstract: An optical phased array (OPA) may be included in a light detection and ranging (LiDAR) system and may be configured to perform beam steering. The OPA may include a cascading structure of splitters configured to enable a branch operation to be performed M times. Each splitter may split an input optical signal in a ratio of 1:1 and output the split input optical signal. The OPA may include a plurality of sets of first phase shifters (PSs), each set of first PSs located exclusively on one output end of a separate splitter, each set of first PSs including a particular quantity of first PSs based on a branch position at which the separate splitter is located. The OPA may be included in a LiDAR system that is further included in a vehicle that is configured to enable navigation of the vehicle, including autonomous navigation, through an environment.

Abstract: A semiconductor device includes a base substrate comprising a first region and a second region, a photonics device disposed in the first region, the photonics device comprising a first doped layer disposed on the base substrate, and a second doped layer disposed on the first doped layer so that at least a portion vertically overlaps the first doped layer, the second doped layer having a first vertical thickness, and a transistor disposed in the second region, the transistor comprising a semiconductor layer disposed on the base substrate and horizontally spaced apart from the first doped layer, and a gate electrode horizontally spaced apart from the second doped layer and disposed on the semiconductor layer, disposed at the same vertical level as that of the second doped layer, and having a second vertical thickness equal to the first vertical thickness.