Patents by Inventor Yong Seok Eun

Yong Seok Eun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9553159
    Abstract: A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: January 24, 2017
    Assignee: SK HYNIX INC.
    Inventors: Kyong Bong Rouh, Yong Seok Eun, Young Jin Son
  • Patent number: 9418891
    Abstract: A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: August 16, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyong-Bong Rouh, Shang-Koon Na, Yong-Seok Eun, Su-Ho Kim, Tae-Han Kim, Mi-Ri Lee
  • Publication number: 20160181159
    Abstract: A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: Sung-Jin WHANG, Moon-Sig JOO, Yong-Seok EUN, Kwon HONG, Bo-Min SEO, Kyoung-Eun CHANG, Seung-Woo SHIN
  • Patent number: 9368586
    Abstract: A transistor including a recessed gate structure having improved doping characteristics and a method for forming such a transistor. The transistor includes a recess in a semiconductor substrate, where the recess is filled with a recessed gate structure including an impurity doped layer and a layer doped with a capture species. The capture species accumulates the impurity and diffuses the impurity to other layers of the recessed gate structure.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyong-Bong Rouh, Yong-Seok Eun, Mi-Ri Lee
  • Publication number: 20160093527
    Abstract: A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.
    Type: Application
    Filed: December 8, 2015
    Publication date: March 31, 2016
    Inventors: Kyong-Bong ROUH, Shang-Koon NA, Yong-Seok EUN, Su-Ho KIM, Tae-Han KIM, Mi-Ri LEE
  • Patent number: 9275904
    Abstract: A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: March 1, 2016
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Jin Whang, Moon-Sig Joo, Yong-Seok Eun, Kwon Hong, Bo-Min Seo, Kyoung-Eun Chang, Seung-Woo Shin
  • Publication number: 20160056258
    Abstract: A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.
    Type: Application
    Filed: November 3, 2015
    Publication date: February 25, 2016
    Inventors: Kyong Bong ROUH, Yong Seok EUN, Young Jin SON
  • Patent number: 9236263
    Abstract: A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 12, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyong-Bong Rouh, Shang-Koon Na, Yong-Seok Eun, Su-Ho Kim, Tae-Han Kim, Mi-Ri Lee
  • Patent number: 8912064
    Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventors: Yong Seok Eun, Tae Kyun Kim, Kyong Bong Rouh, Eun Shil Park
  • Patent number: 8859370
    Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: October 14, 2014
    Assignee: SK Hynix Inc.
    Inventors: Yong Seok Eun, Tae Kyun Kim, Kyong Bong Rouh, Eun Shil Park
  • Publication number: 20140030884
    Abstract: A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.
    Type: Application
    Filed: December 18, 2012
    Publication date: January 30, 2014
    Applicant: SK HYNIX INC.
    Inventors: Kyong-Bong ROUH, Shang-Koon NA, Yong-Seok EUN, Su-Ho KIM, Tae-Han KIM, Mi-Ri LEE
  • Publication number: 20140001541
    Abstract: A transistor including a recessed gate structure having improved doping characteristics and a method for forming such a transistor. The transistor includes a recess in a semiconductor substrate, where the recess is filled with a recessed gate structure including an impurity doped layer and a layer doped with a capture species. The capture species accumulates the impurity and diffuses the impurity to other layers of the recessed gate structure.
    Type: Application
    Filed: December 19, 2012
    Publication date: January 2, 2014
    Applicant: SK HYNIX INC.
    Inventors: Kyong-Bong ROUH, Yong-Seok EUN, Mi-Ri LEE
  • Publication number: 20130288442
    Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Inventors: Yong Seok EUN, Tae Kyun KIM, Kyong Bong ROUH, Eun Shil PARK
  • Publication number: 20130288441
    Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Inventors: Yong Seok EUN, Tae Kyun Kim, Kyong Bong Rouh, Eun Shil Park
  • Patent number: 8513103
    Abstract: A buried junction is formed in a vertical transistor of a semiconductor device. Wall bodies are formed from a semiconductor substrate, the wall bodies protruding while having a first side surface and a second side surface in the opposite side of the first side surface; forming a one side contact mask having an opening which selectively opens a portion of the first side surface of the wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer by diffusing impurities having different diffusivities into the portion of the first side surface exposed to the opening.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: August 20, 2013
    Assignee: SK Hynix Inc.
    Inventors: Eun Shil Park, Yong Seok Eun, Kyong Bong Rouh
  • Patent number: 8481431
    Abstract: A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 9, 2013
    Assignee: SK Hynix Inc.
    Inventors: Kyong Bong Rouh, Yong Seok Eun, Eun Shil Park
  • Patent number: 8481390
    Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: July 9, 2013
    Assignee: SK Hynix Inc.
    Inventors: Yong Seok Eun, Tae Kyun Kim, Kyong Bong Rouh, Eun Shil Park
  • Publication number: 20130161767
    Abstract: A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.
    Type: Application
    Filed: September 13, 2012
    Publication date: June 27, 2013
    Applicant: SK HYNIX INC.
    Inventors: Kyong Bong ROUH, Yong Seok EUN, Young Jin SON
  • Patent number: 8470664
    Abstract: A dual polysilicon gate is fabricated by, inter alia, forming a polysilicon layer doped with impurities of a first conductivity type on a substrate having a first region and a second region, forming a mask pattern that covers the polysilicon layer in the first region and leaves the polysilicon layer in the second region, injecting impurities of a second conductivity type into the polysilicon layer in the second region left exposed by the mask pattern. Removing the mask pattern, and patterning the polysilicon layer to form a first polysilicon pattern in the first region and a second polysilicon pattern in the second region. The second polysilicon pattern is formed to have protrusions that laterally protrude from sidewalls thereof. Subsequently, impurities of the second conductivity type are injected into the substrate in the second region and into the protrusions of the second polysilicon pattern.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: June 25, 2013
    Assignee: SK Hynix Inc.
    Inventors: Kyong Bong Rouh, Yong Seok Eun
  • Patent number: 8431981
    Abstract: A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: April 30, 2013
    Assignee: SK Hynix Inc.
    Inventors: Baek Mann Kim, Jun Ki Kim, Yong Seok Eun, Kyong Bong Rouh