Abstract: Provided is a wastewater purification method, the method including: supplying a first mixed stream, in which an acid component and wastewater including water, a nitrile-based monomer, and ammonia are mixed, to a first column; recovering the nitrile-based monomer from an upper discharge stream from the first column; supplying a second mixed stream, in which a lower discharge stream from the first column and a base component are mixed, to a second column; and recovering the ammonia from an upper discharge stream from the second column and separating purified wastewater.

Abstract: A refrigerant module for a vehicle includes: a heat exchanger for exchanging heat between a refrigerant introduced therein and a working fluid; a valve manifold connected to the heat exchanger and having a refrigerant flow path formed inside to supply the refrigerant to the heat exchanger or to bypass the refrigerant; and a plurality of valve assemblies mounted on the valve manifold to control a flow of the refrigerant flowing in the refrigerant flow path.

Abstract: A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones. The controller is configured to receive a program request related to at least one application program executed by a host, to determine at least one zone designated by the at least one application program as an open state, and to control the memory device to perform a program operation on at least one memory block allocated for an open state zone.

Abstract: An ICS repeater usable in a wireless network and, more specifically, a method for effectively canceling only an interference signal by selectively using an autocorrelation canceller in an ICS repeater are described. According to one aspect, a method for canceling interference performed by a 5G ICS repeater may comprise obtaining a first error signal by removing a first predicted feedback signal from a first original signal received through a reception antenna; generating a first delay signal by delaying the first error signal; determining whether the first original signal is a null signal based on magnitude information of the first error signal; determining a first reference signal based on the first delay signal according to a determination result of whether the first original signal is a null signal; and generating a second predicted feedback signal based on the first reference signal.

Abstract: The present invention relates to a multi-nozzle for supplying CMP slurry. An exemplary embodiment of the present invention drops the slurry from the center of a pad to the outside through a plurality of spray nozzles, thereby increasing the efficiency of a planarization process by evenly spreading the slurry over the entire pad and reducing costs by minimizing the amount of slurry wasted.

Abstract: A method and a system thereof for producing a digital holographic screen based on multi-hogel printing are proposed. The system includes a light source unit including lasers, a dichroic mirror for RGB three color matching, mirrors, a beam splitter, and an optical shutter, an object beam unit including a spatial filter, a lens, and a mirror, a reference beam unit including a spatial filter, a lens, and a mirror, a diffuser fixing unit including a diffuser holder and a diffuser positioned between the object beam unit and a recording material and configured to scatter and diffuse the object beam, a photomask movement unit including a photomask holder, an XY-translation stage, and a photomask positioned between the reference beam unit and the recording medium and on which a grid-shaped on/off binary pattern is printed, and a controller configured to control the optical shutter and the XY-translation stage.

Abstract: Disclosed is a technology of extracting faradaic current-type Second-Derivative-based Background Removal (SDBR) data, from which a capacitive charge current is subtracted, through the second derivative after background subtraction of FSCV data and providing a neurotransmitter concentration measurement result based on the extracted SDBR data.

Abstract: A method for operating a multi-transaction memory system, the method includes: storing Logical Block Address (LBA) information changed in response to a request from a host and a transaction identification (ID) of the request into one page of a memory block; and performing a transaction commit in response to a transaction commit request including the transaction ID from the host, wherein the performing of the transaction commit includes: changing a valid block bitmap in a controller of the multi-transaction memory system based on the LBA information.

Abstract: The present disclosure relates to a secondary battery, which can improve the sealing efficiency of a can (or case). The secondary battery includes an electrode assembly; a case configured to accommodate the electrode assembly, the case including a bottom portion, long side portions and short side portions, at least one of which includes a welding portion that is configured to be bent and welded, and a cap plate coupled to the case, wherein a portion of the welding portion is overlap-welded.

Abstract: The present disclosure relates to a secondary battery, which can improve the sealing efficiency of a can (or case). The secondary battery includes an electrode assembly; a case configured to accommodate the electrode assembly, the case including a bottom portion, long side portions and short side portions, at least one of which includes a welding portion that is configured to be bent and welded, and a cap plate coupled to the case, wherein a portion of the welding portion is overlap-welded.

Abstract: A memory system includes a nonvolatile memory set including a nonvolatile memory; and a memory controller configured to control the nonvolatile memory set. The memory controller may write data to a memory block in a target memory block pool in the nonvolatile memory set during a target time period existing between a time at which an operation mode for the nonvolatile memory set is changed from a second operation mode to a first operation mode and a time at which a command including information indicating that a host expects a requested operation to be performed in the first operation mode is received from the host, prevent execution of a background operation for the nonvolatile memory set, when the operation mode is the first operation mode, and control a background operation for the nonvolatile memory set to be executable, when the operation mode is the second operation mode.

Abstract: A memory system includes a first memory device including a plurality of first physical blocks; a second memory device including a plurality of second physical blocks; a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to the plurality of first physical blocks; a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to the plurality of second physical blocks; a global wear-leveling manager suitable for changing mapping between the first physical blocks, which are mapped to one among the first super blocks, and the second physical blocks, which are mapped to one among the second super blocks based on degrees of wear of the first and second super blocks.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.

Abstract: A case for a secondary battery includes: a body plate including a bottom portion, first side portions bent and extended from the bottom portion in opposite directions, and extending portions bent from at least one selected from the bottom portion and the first side portions to then be extended; and second side portions coupled to the extending portions. A secondary battery includes an electrode assembly; the case accommodating the electrode assembly; and a cap assembly coupled to the case to seal the case.

Abstract: A secondary battery includes: an electrode assembly; a case accommodating the electrode assembly, and a cap assembly coupled to the case to seal the case, and the case includes a bottom portion, long side portions bent and extended from the bottom portion, a first short side portion bent and extended from the bottom portion, second short side portions bent and extended from the long side portions, the first short side portion and the second short side portions connected to each other to define a short side portion, and protrusions located between the first short side portion and the second short side portions.

Abstract: A memory system includes: a plurality of memory devices; a plurality of cores suitable for controlling the plurality of memory devices, respectively; and a controller including: a host interface layer for providing any one of the cores with a request of a host based on mapping between logical addresses and the cores, a remap manager for changing the mapping between the logical addresses and the cores in response to a trigger, a data swapper for swapping data between the plurality of memory devices based on the changed mapping, and a state manager for determining a state of the memory system depending on whether the data swapper is swapping the data or has completed swapping the data, and providing the remap manager with the trigger based on the state of the memory system and a difference in a degree of wear between the plurality of memory devices.

Abstract: A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones. The controller is configured to receive a program request related to at least one application program executed by a host, to determine at least one zone designated by the at least one application program as an open state, and to control the memory device to perform a program operation on at least one memory block allocated for an open state zone.

Abstract: A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones. The controller is configured to receive a program request related to at least one application program executed by a host, to determine at least one zone designated by the at least one application program as an open state, and to control the memory device to perform a program operation on at least one memory block allocated for an open state zone.

Abstract: A method for operating a multi-transaction memory system, the method includes: storing Logical Block Address (LBA) information changed in response to a request from a host and a transaction identification (ID) of the request into one page of a memory block; and performing a transaction commit in response to a transaction commit request including the transaction ID from the host, wherein the performing of the transaction commit includes: changing a valid block bitmap in a controller of the multi-transaction memory system based on the LBA information.

Abstract: Provided are: a peptide for regulating reactivity to a serotonin reuptake inhibitor-based antidepressant; a vector and a pharmaceutical composition for preventing or treating depression, which comprise same; a method for screening for an antidepressant by evaluating the activity of mossy cells; and the like.