Abstract: Provided is a memory system coupled to a plurality of hosts each including an FTL. The memory system may include: a controller suitable for allowing only a write request to be received from any one of the plurality of hosts, when a write lock for a write request from the any one host is set; and a memory device controlled by the controller, and suitable for performing a write operation according to the write request from the any one host, wherein the controller includes: a lock manager suitable for setting a write lock depending on whether a lock is set in the memory device, and releasing the write lock when the write operation is completed; and a sync manager suitable for controlling synchronization of FTL metadata of the FTLs of the other hosts excluding the any one host, according to whether the write operation is successfully performed.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.

Abstract: The memory controller controls at least one memory device including a plurality of stream storage areas. The memory controller comprises a buffer, a write history manager, a write controller, and a garbage collection controller. The buffer stores write data. The write history manager stores write count values for each of the plurality of stream storage areas and generates write history information indicating a write operation frequency for each of the plurality of stream storage areas based on the write count values. The write controller controls the at least one memory device to store the write data provided from the buffer. The garbage collection controller controls the at least one memory device to perform a garbage collection operation on a target stream storage area selected from among the plurality of stream storage areas based on the write history information.

Abstract: A method for operating a multi-transaction memory system, the method includes: storing Logical Block Address (LBA) information changed in response to a request from a host and a transaction identification (ID) of the request into one page of a memory block; and performing a transaction commit in response to a transaction commit request including the transaction ID from the host, wherein the performing of the transaction commit includes: changing a valid block bitmap in a controller of the multi-transaction memory system based on the LBA information.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.

Abstract: A memory system includes: a plurality of memory devices; a plurality of cores suitable for controlling the plurality of memory devices, respectively; and a controller including: a host interface layer for providing any one of the cores with a request of a host based on mapping between logical addresses and the cores, a remap manager for changing the mapping between the logical addresses and the cores in response to a trigger, a data swapper for swapping data between the plurality of memory devices based on the changed mapping, and a state manager for determining a state of the memory system depending on whether the data swapper is swapping the data or has completed swapping the data, and providing the remap manager with the trigger based on the state of the memory system and a difference in a degree of wear between the plurality of memory devices.

Abstract: A memory system includes a first memory device including a plurality of first physical blocks; a second memory device including a plurality of second physical blocks; a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to the plurality of first physical blocks; a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to the plurality of second physical blocks; a global wear-leveling manager suitable for changing mapping between the first physical blocks, which are mapped to one among the first super blocks, and the second physical blocks, which are mapped to one among the second super blocks based on degrees of wear of the first and second super blocks.

Abstract: Provided are: a peptide for regulating reactivity to a serotonin reuptake inhibitor-based antidepressant; a vector and a pharmaceutical composition for preventing or treating depression, which comprise same; a method for screening for an antidepressant by evaluating the activity of mossy cells; and the like.

Abstract: A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones. The controller is configured to receive a program request related to at least one application program executed by a host, to determine at least one zone designated by the at least one application program as an open state, and to control the memory device to perform a program operation on at least one memory block allocated for an open state zone.

Abstract: The memory controller controls at least one memory device including a plurality of stream storage areas. The memory controller comprises a buffer, a write history manager, a write controller, and a garbage collection controller. The buffer stores write data. The write history manager stores write count values for each of the plurality of stream storage areas and generates write history information indicating a write operation frequency for each of the plurality of stream storage areas based on the write count values. The write controller controls the at least one memory device to store the write data provided from the buffer. The garbage collection controller controls the at least one memory device to perform a garbage collection operation on a target stream storage area selected from among the plurality of stream storage areas based on the write history information.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Abstract: A memory system includes a nonvolatile memory set including a nonvolatile memory; and a memory controller configured to control the nonvolatile memory set. The memory controller may write data to a memory block in a target memory block pool in the nonvolatile memory set during a target time period existing between a time at which an operation mode for the nonvolatile memory set is changed from a second operation mode to a first operation mode and a time at which a command including information indicating that a host expects a requested operation to be performed in the first operation mode is received from the host, prevent execution of a background operation for the nonvolatile memory set, when the operation mode is the first operation mode, and control a background operation for the nonvolatile memory set to be executable, when the operation mode is the second operation mode.

Abstract: A case for a secondary battery includes: a body plate including a bottom portion, first side portions bent and extended from the bottom portion in opposite directions, and extending portions bent from at least one selected from the bottom portion and the first side portions to then be extended; and second side portions coupled to the extending portions. A secondary battery includes an electrode assembly; the case accommodating the electrode assembly; and a cap assembly coupled to the case to seal the case.

Abstract: The present disclosure relates to a secondary battery, which can improve the sealing efficiency of a can (or case). The secondary battery includes an electrode assembly; a case configured to accommodate the electrode assembly, the case including a bottom portion, long side portions and short side portions, at least one of which includes a welding portion that is configured to be bent and welded, and a cap plate coupled to the case, wherein a portion of the welding portion is overlap-welded.

Abstract: A secondary battery includes: an electrode assembly; a case accommodating the electrode assembly, and a cap assembly coupled to the case to seal the case, and the case includes a bottom portion, long side portions bent and extended from the bottom portion, a first short side portion bent and extended from the bottom portion, second short side portions bent and extended from the long side portions, the first short side portion and the second short side portions connected to each other to define a short side portion, and protrusions located between the first short side portion and the second short side portions.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

Abstract: Provided is a memory system coupled to a plurality of hosts each including an FTL. The memory system may include: a controller suitable for allowing only a write request to be received from any one of the plurality of hosts, when a write lock for a write request from the any one host is set; and a memory device controlled by the controller, and suitable for performing a write operation according to the write request from the any one host, wherein the controller includes: a lock manager suitable for setting a write lock depending on whether a lock is set in the memory device, and releasing the write lock when the write operation is completed; and a sync manager suitable for controlling synchronization of FTL metadata of the FTLs of the other hosts excluding the any one host, according to whether the write operation is successfully performed.

Abstract: A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.