Abstract: Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

Abstract: A system in package and method of making as system in package are disclosed. The system in package has a substrate (102) with a plurality of passive devices (104) mounted thereon. A molding compound (106) envelopes the plurality of passive devices (104) to define a flat surface (116) substantially parallel to a surface of the substrate (102). A plurality of integrated circuit dies (110) is coupled successively to the flat surface (116).

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

Abstract: A design console provides interaction with a developer in a graphical interface of a virtual agent programming system where elements of an intended dialog between the virtual agent and a chat (developer) user are shown as dialog boxes in the graphical interface, including a trigger element which processes and detects from the input messages processed an intent by the chat user to invoke the virtual agent based on one or more stored utterances; an interaction module which sends a virtual agent message to the chat user, and receives therefrom an utterance responsive to the virtual agent message; and an action element that carries out a specified user intent based on the values of the parameters converted by the interaction module from the utterance collected from the chat user.

Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

Abstract: Techniques for providing an integrated circuit package that avoids or eliminates x-y area and z-height compared to conventional integrated circuit packages. In certain examples, an example package can utilize a substrate with an opening and bottom side or sidewall terminations to avoid adding addition x-y substrate area or z-axis package height associated with an integrated circuit die of a stack of integrated circuit dies of the package.

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

Abstract: Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag).

Abstract: A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

Abstract: An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.