Abstract: An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.

Abstract: Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag).

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution Layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

Abstract: A system in package and method of making as system in package are disclosed. The system in package has a substrate (102) with a plurality of passive devices (104) mounted thereon. A molding compound (106) envelopes the plurality of passive devices (104) to define a flat surface (116) substantially parallel to a surface of the substrate (102). A plurality of integrated circuit dies (110) is coupled successively to the flat surface (116).

Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a plurality of dies stacked on a substrate and a reference die on the plurality of dies and having a fiducial marker that indicates a spatial position of the plurality of dies for alignment of an electronics assembly tool. The fiducial marker can comprise a physical alteration of the reference die, such as indicia that is sawed or laser/plasma/chemical etched. A transparent dielectric layer is disposed on the reference die such that the tool can locate the fiducial marker in three dimensional space through the transparent layer. The dielectric layer is etched corresponding to a photomask after a photoresist is disposed on the dielectric layer. The etched dielectric layer comprises at least one redistribution layer electrically coupled to the vertical wire interconnect structure to provide an ultra-thin package. A method of aligning an electronics assembly tool is disclosed.

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate, an electronic component, a mold compound encapsulating the electronic component, and a redistribution layer disposed such that the mold compound is between the package substrate and the redistribution layer. The redistribution layer and the package substrate can be electrically coupled. In addition, the redistribution layer and the electronic component can be electrically coupled to electrically couple the electronic component and the package substrate. Associated systems and methods are also disclosed.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

Abstract: A thermoplastic composition comprising a polyethylene terephthalate having chemically incorporated within the polyethylene terephthalate a) crystallinity reducing amount of an isophathalic acid, or a crystallinity reducing amount of diethylene glycol, or a crystallinity reducing amount of a combination of an isophathalic acid and diethylene glycol thereby making a modified polyethylene terephthalate; b) a chain extending agent which has reacted with a carboxy end group or an alcohol end group, and c) an amount of at least one antiblocking agent that maintains the neck opening of a parison formed from the composition, the parison surrounding a capacitor.