Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate.

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

Abstract: A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: A memory device and a manufacturing method are provided. The method includes: forming a first conductive pattern on a substrate; forming an active structure over the first conductive pattern, wherein the active structure comprises a gate pattern, a channel pillar and a charge storage layer, the channel pillar penetrates the gate pattern and electrically connects with the first conductive pattern, and the charge storage layer is disposed between the gate pattern and the channel pillar; forming a second conductive pattern over the active structure, wherein the second conductive pattern is electrically connected with the channel pillar; and performing formation of the active structure one more time, such that the channel pillars of the active structures are vertically spaced apart from each other, and electrically connected to the second conductive pattern extending in between the channel pillars.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a plurality of memory cells stacked on a substrate. The memory cell includes two conductive patterns, a channel pillar, a gate pattern and a charge storage layer. The two conductive patterns are stacked on the substrate. The channel pillar extends between the two conductive patterns along a stacking direction of the two conductive patterns, and is electrically connected with the two conductive patterns. The gate pattern is disposed between the two conductive patterns and located at a sidewall of the channel pillar. The charge storage layer is disposed between the gate pattern and the channel pillar.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a plurality of memory cells stacked on a substrate. The memory cell includes two conductive patterns, a channel pillar, a gate pattern and a charge storage layer. The two conductive patterns are stacked on the substrate. The channel pillar extends between the two conductive patterns along a stacking direction of the two conductive patterns, and is electrically connected with the two conductive patterns. The gate pattern is disposed between the two conductive patterns and located at a sidewall of the channel pillar. The charge storage layer is disposed between the gate pattern and the channel pillar.

Abstract: Provided is scissors comprising a movable first handle unit; a stationary second handle unit including a bifurcated jaw, a pivotal blade in the jaw, a spring biased pivotal plate member in the jaw and including teeth, a gear and ratchet wheel assembly, and a spring biased pivotal pawl; and a spring biased lever including a pawl member engaged with the ratchet wheel. Continuously pivoting the first handle unit about the second handle unit by moving the first handle unit alternately back and forth in each action of pivoting the first handle unit toward the second handle unit will pivot the first and second protrusions counterclockwise, rotate the gear and ratchet assembly clockwise, and pivot the teeth counterclockwise to cut a pipe anchored in the mouth.