Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

Abstract: A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.

Abstract: A method for identifying a pseudo wireless access point, applied to an electronic device, includes: determining whether an abnormal file operation is detected, when the electronic device is connected to a wireless network through a wireless access point; determining the wireless access point to be a pseudo wireless access point, when the abnormal file operation is detected; and executing an early warning instruction. A system for identifying a pseudo wireless access point is also provided. The present disclosure can timely discover a phishing wireless access point and prevent loss of a user's privacy and property.

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: A method and apparatus for annotating video is provided herein. During the process of annotating a video, a skipped portion of video will be analyzed for predetermined events or items. The video immediately following the skipped video will be annotated based on the analysis of the skipped video. The annotation process results in text being added to the video explaining and/or commenting on the predetermined events or items being detected within the skipped video.

Abstract: A memory device and a manufacturing method are provided. The method includes: forming a first conductive pattern on a substrate; forming an active structure over the first conductive pattern, wherein the active structure comprises a gate pattern, a channel pillar and a charge storage layer, the channel pillar penetrates the gate pattern and electrically connects with the first conductive pattern, and the charge storage layer is disposed between the gate pattern and the channel pillar; forming a second conductive pattern over the active structure, wherein the second conductive pattern is electrically connected with the channel pillar; and performing formation of the active structure one more time, such that the channel pillars of the active structures are vertically spaced apart from each other, and electrically connected to the second conductive pattern extending in between the channel pillars.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a plurality of memory cells stacked on a substrate. The memory cell includes two conductive patterns, a channel pillar, a gate pattern and a charge storage layer. The two conductive patterns are stacked on the substrate. The channel pillar extends between the two conductive patterns along a stacking direction of the two conductive patterns, and is electrically connected with the two conductive patterns. The gate pattern is disposed between the two conductive patterns and located at a sidewall of the channel pillar. The charge storage layer is disposed between the gate pattern and the channel pillar.

Abstract: A remote wakeup method includes: receiving a wakeup request packet from a first apparatus, obtaining a wakeup information according to the wakeup request packet, generating an apparatus wakeup packet according to the wakeup request packet and the wakeup information, obtaining a connection information corresponding to a second apparatus according to the wakeup request packet, and sending the apparatus wakeup packet to the second apparatus based on the connection information. The wakeup request packet includes a device identifier (UID) of the second apparatus, and the apparatus wakeup packet includes the device identifier of the second apparatus and wakeup information.

Abstract: The present invention provides a novel method for multiple labelling of nucleic acid probes by ligation. The method uses a ligase catalysed reaction to connect a nucleic acid probe with multiple pre-prepared nucleic acid label carrier molecules under the presence of a stabilizing complementary adaptor oligonucleotide. The method allows for an easy, cheap and fast labelling of multiple probes with multiple different labels. In this way, the costs and effort for the generation of single molecule Fluorescent In Situ Hybridization (smFISH) assays was significantly reduced, allowing combinatorial multi-color barcoding of nucleic acid probes The invention further provides methods for the generation of FISH libraries and labelling kits comprising the novel tools of the invention.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a plurality of memory cells stacked on a substrate. The memory cell includes two conductive patterns, a channel pillar, a gate pattern and a charge storage layer. The two conductive patterns are stacked on the substrate. The channel pillar extends between the two conductive patterns along a stacking direction of the two conductive patterns, and is electrically connected with the two conductive patterns. The gate pattern is disposed between the two conductive patterns and located at a sidewall of the channel pillar. The charge storage layer is disposed between the gate pattern and the channel pillar.

Abstract: A hydrogel composite is provided. The hydrogel composite comprises a modified poloxamer having a first charge moiety and a peptide having a second charge moiety, wherein the first charge moiety and the second charge moiety are oppositely charged for ionic interaction between the modified poloxamer and the peptide, and wherein at least one of the modified poloxamer and the peptide comprises a crosslinkable moiety. In particular, the modified poloxamer is a pluronic monocarboxylate activated by dimethylaminopyridine and triethanolamine; the peptide is a gelatin methacrylate. A bioshaping method using the hydrogel composite is provided, as well as a three-dimensional network obtained by the bioshaping method.

Abstract: An electric tool and a motor drive system are provided. The motor drive system includes a trigger switch, an electronic switch, and a switch control circuit connected between the trigger switch and the electronic switch. The trigger switch is connected in series to a power supply. The electronic switch is configured to control a motor to be powered on or powered off. The switch control circuit is configured to control the electronic switch based on a state of the trigger switch, wherein the electronic switch is delayed to be turned off after the trigger switch is turned off to control the motor to be powered off later than a time that the trigger switch is turned off.

Abstract: The present invention provides a novel method for labelling nucleic acid probes. The method uses a ligase catalysed reaction to connect a nucleic acid probe with pre-prepared nucleic acid label carrier molecules under the presence of a stabilizing complementary splint oligonucleotide. The method allows for an easy, cheap and fast labelling of multiple probes with multiple different labels. In this way, the costs and effort for the generation of single molecule Fluorescent In Situ Hybridization (smFISH) assays was significantly reduced. The invention further provides methods for the generation of FISH libraries and labelling kits comprising the novel tools of the invention.

Abstract: A camera principal point automatic calibration system including an image acquiring device, a controller, a first display and a second display is provided, wherein the controller controls the first and second display to display parallel first line and second line. The controller selectively rotates the first and second line according to whether a first and second image line generated by the image acquiring device corresponding to the first and second line are parallel or not, and the controller calculates the principal point from parallel first image line and second image line.

Abstract: A method for estimating epipolar geometry and to be performed by a processing module includes the steps of: A) choosing, in each first and third images captured by a first image capturing module, two points which are collinear with a corresponding one of a first reference object in the first image and a second reference object in the third image, such that in each second and fourth images captured by a second image capturing module, two points corresponding to the two points chosen in a respective one of the first and third images are collinear with a corresponding one of the first reference object in the second image and the second reference object in the fourth image; and B) determining first and second epipoles based on the aforementioned points.

Abstract: A method for identifying a pseudo wireless access point, applied to an electronic device, includes: determining whether an abnormal file operation is detected, when the electronic device is connected to a wireless network through a wireless access point; determining the wireless access point to be a pseudo wireless access point, when the abnormal file operation is detected; and executing an early warning instruction. A system for identifying a pseudo wireless access point is also provided. The present disclosure can timely discover a phishing wireless access point and prevent loss of a user's privacy and property.