Abstract: A printing control terminal apparatus, an image forming apparatus, and a method of controlling the same. The printing control terminal apparatus includes a communication interface to receive job log data from the image forming apparatus, a storage device to store the received job log data, and a controller to extract job accumulation amounts and job quantities, which belong to the same job type, from the job log data in a time order, and to determine whether the job log data has been lost based on the extracted job accumulation amounts and job quantities.

Abstract: Disclosed are a host apparatus connected to an image forming apparatus and an information displaying method thereof. An information displaying method of a host apparatus which receives a data of at least one image forming apparatus including: receiving a data of the image forming apparatus; displaying a User Interface (UI) screen including a data area displaying the data by item and a graphic area displaying a graph of the data in the data area; adding a data of an item in the data area to the graphic area; determining whether the data of the item added is graphicalizable; and graphicalizing and displaying the data of the item added in the graphic area according to the determination result. With this, the host apparatus provides a user with convenience in facilitating graph reprocessing and data expansion as the user needs with regard to a web solution or an application to control information of the image forming apparatus.

Abstract: A printing control terminal apparatus, an image forming apparatus, and a method of controlling the same. The printing control terminal apparatus includes a communication interface to receive job log data from the image forming apparatus, a storage device to store the received job log data, and a controller to extract job accumulation amounts and job quantities, which belong to the same job type, from the job log data in a time order, and to determine whether the job log data has been lost based on the extracted job accumulation amounts and job quantities.

Abstract: An apparatus to manage an account is provided. The account managing apparatus includes an account management unit which manages a user account of at least one user who uses an image forming apparatus, a storage unit which stores guest information related to the user account, a guest account generating unit which generates a guest account dependent on the user account based on stored guest information and the user account when a request to generate an account to use the image forming apparatus is received from a guest, and a control unit which controls the image forming apparatus according to a generated account policy.

Abstract: A method of fabricating a non-volatile memory device is provided. The method includes sequentially forming a tunnel insulation layer and a first polysilicon layer on a substrate, patterning the first polysilicon layer and the tunnel insulation layer, forming a dielectric layer to cover the patterned first polysilicon layer and the patterned tunnel insulation layer, forming a gate insulation layer on the substrate where the substrate is exposed, forming a second polysilicon layer to cover the dielectric layer, and forming a first floating gate and a second floating gate a fixed distance apart from each other, the forming of the first and second floating gates including etching middle portions of the second polysilicon layer, the dielectric layer, the patterned first polysilicon layer, and the patterned tunnel insulation layer, and separating the etched layers into two parts.

Abstract: Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.

Abstract: A method of fabricating a non-volatile memory device is provided. The method includes sequentially forming a tunnel insulation layer and a first polysilicon layer on a substrate, patterning the first polysilicon layer and the tunnel insulation layer, forming a dielectric layer to cover the patterned first polysilicon layer and the patterned tunnel insulation layer, forming a gate insulation layer on the substrate where the substrate is exposed, forming a second polysilicon layer to cover the dielectric layer, and forming a first floating gate and a second floating gate a fixed distance apart from each other, the forming of the first and second floating gates including etching middle portions of the second polysilicon layer, the dielectric layer, the patterned first polysilicon layer, and the patterned tunnel insulation layer, and separating the etched layers into two parts.

Abstract: A non-volatile memory device having a split gate type cell structure, a method for fabricating the same, and a method for fabricating a semiconductor device by using the same are provided. A non-volatile memory device includes a substrate, a plurality of patterned tunnel insulation layers formed on the substrate, a plurality of floating gates formed on the patterned tunnel insulation layers, a plurality of patterned dielectric layers to cover upper portions and sidewalls of the floating gates, a plurality of selection gates formed on sidewalls of the patterned dielectric layers, and a plurality of source/drain regions formed in the substrate exposed at one sides of the selection gates and one sides of the floating gates.

Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate.

Abstract: An apparatus to manage an account is provided. The account managing apparatus includes an account management unit which manages a user account of at least one user who uses an image forming apparatus, a storage unit which stores guest information related to the user account, a guest account generating unit which generates a guest account dependent on the user account based on stored guest information and the user account when a request to generate an account to use the image forming apparatus is received from a guest, and a control unit which controls the image forming apparatus according to a generated account policy.

Abstract: Disclosed are a host apparatus connected to an image forming apparatus and an information displaying method thereof. An information displaying method of a host apparatus which receives a data of at least one image forming apparatus including: receiving a data of the image forming apparatus; displaying a User Interface (UI) screen including a data area displaying the data by item and a graphic area displaying a graph of the data in the data area; adding a data of an item in the data area to the graphic area; determining whether the data of the item added is graphicalizable; and graphicalizing and displaying the data of the item added in the graphic area according to the determination result. With this, the host apparatus provides a user with convenience in facilitating graph reprocessing and data expansion as the user needs with regard to a web solution or an application to control information of the image forming apparatus.

Abstract: Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.

Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate.

Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer covering the gate structures and active regions located at each side of the gate structures; forming a second electrode layer over the first insulation layer; and forming a plurality of control gates on the active regions located at each side of the gate structures by performing an etch-back process to the second electrode layer.

Abstract: A method for fabricating a semiconductor device for a system on chip (SOC) for embodying a transistor for a logic device, an electrical erasable programmable read only memory (EEPROM) cell and a flash memory cell in one chip is provided. Floating gates of the EEPROM cell and the flash memory cell are formed by using a first polysilicon layer; and a gate electrode of the logic device and control gates of the EEPROM cell and the flash memory cell are formed by using a second polysilicon layer. Thus, it is possible to stably form the logic device, the EEPROM cell and the flash memory cell in one chip.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal process to form junction regions between the trenches in the substrate by diffusing the impurities and simultaneously to form a gate oxide layer on the substrate and on the junction regions; forming a polysilicon layer on the gate oxide layer; sequentially etching the polysilicon layer and the gate oxide layer to form a gate structure, and to form first spacers on lateral walls of the junction regions; forming second spacers on lateral walls of the first spacers and the gate structure; and forming a metal silicide layer on top portions of the junction regions and the gate structure.

Abstract: A method for fabricating a semiconductor device for a system on chip (SOC) for embodying a transistor for a logic device, an electrical erasable programmable read only memory (EEPROM) cell and a flash memory cell in one chip is provided. Floating gates of the EEPROM cell and the flash memory cell are formed by using a first polysilicon layer; and a gate electrode of the logic device and control gates of the EEPROM cell and the flash memory cell are formed by using a second polysilicon layer. Thus, it is possible to stably form the logic device, the EEPROM cell and the flash memory cell in one chip.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal process to form junction regions between the trenches in the substrate by diffusing the impurities and simultaneously to form a gate oxide layer on the substrate and on the junction regions; forming a polysilicon layer on the gate oxide layer; sequentially etching the polysilicon layer and the gate oxide layer to form a gate structure, and to form first spacers on lateral walls of the junction regions; forming second spacers on lateral walls of the first spacers and the gate structure; and forming a metal silicide layer on top portions of the junction regions and the gate structure.

Abstract: A non-volatile memory device having a split gate type cell structure, a method for fabricating the same, and a method for fabricating a semiconductor device by using the same are provided. A non-volatile memory device includes a substrate, a plurality of patterned tunnel insulation layers formed on the substrate, a plurality of floating gates formed on the patterned tunnel insulation layers, a plurality of patterned dielectric layers to cover upper portions and sidewalls of the floating gates, a plurality of selection gates formed on sidewalls of the patterned dielectric layers, and a plurality of source/drain regions formed in the substrate exposed at one sides of the selection gates and one sides of the floating gates.

Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate.