Abstract: A non-volatile memory device having a split gate type cell structure, a method for fabricating the same, and a method for fabricating a semiconductor device by using the same are provided. A non-volatile memory device includes a substrate, a plurality of patterned tunnel insulation layers formed on the substrate, a plurality of floating gates formed on the patterned tunnel insulation layers, a plurality of patterned dielectric layers to cover upper portions and sidewalls of the floating gates, a plurality of selection gates formed on sidewalls of the patterned dielectric layers, and a plurality of source/drain regions formed in the substrate exposed at one sides of the selection gates and one sides of the floating gates.

Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate.

Abstract: A method is disclosed for fabricating an MDL (Merged DRAM Logic) semiconductor device, in which silicide is formed on a logic region and a memory region selectively for enhancing device reliability. The method includes the steps of (a) providing a substrate having a first region and a second region adjoining the first region, (b) forming a first gate forming material layer in the first region, (c) forming a second gate forming material layer in the first region having the first gate forming material layer formed therein and the second region, (d) selectively patterning the second gate forming material layer to form second gates in the second region and a boundary dummy pattern layer at a boundary area of the first and second regions, and (e) selectively patterning the first gate forming material layer to form first gates in the first region.

Abstract: A method for manufacturing a semiconductor device having a first capacitor in a memory cell region and a second capacitor in a logic region is described. The method includes the steps of: a) forming an interlayer insulating layer on a blanket substrate; b) simultaneously forming a first opening portion and a second opening portion for the first capacitor and the second capacitor, respectively, by selectively etching the interlayer insulating layer; c) simultaneously forming bottom electrodes of the first capacitor and the second capacitor by forming a conductive layer within the first opening portion and the second opening portion; d) forming a dielectric layer on the bottom electrodes of the first capacitor and the second capacitor; and e) forming top electrodes of the first capacitor and the second capacitor on the dielectric layer.

Abstract: A method for manufacturing a semiconductor device having a first capacitor in a memory cell region and a second capacitor in a logic region. The method includes the steps of: a) forming an interlayer insulating layer on a blanket substrate; b) simultaneously forming a first opening portion and a second opening portion for the first capacitor and the second capacitor, respectively, by selectively etching the interlayer insulating layer; c) simultaneously forming bottom electrodes of the first capacitor and the second capacitor by forming a conductive layer within the first opening portion and the second opening portion; d) forming a dielectric layer on the bottom electrodes of the first capacitor and the second capacitor; and e) forming top electrodes of the first capacitor and the second capacitor on the dielectric layer.

Abstract: A method is disclosed for fabricating an MDL (Merged DRAM Logic) semiconductor device, in which suicide is formed on a logic region and a memory region selectively for enhancing device reliability. The method includes the steps of (a) providing a substrate having a first region and a second region adjoining the first region, (b) forming a first gate forming material layer in the first region, (c) forming a second gate forming material layer in the first region having the first gate forming material layer formed therein and the second region, (d) selectively patterning the second gate forming material layer to form second gates in the second region and a boundary dummy pattern layer at a boundary area of the first and second regions, and (e) selectively patterning the first gate forming material layer to form first gates in the first region.