Patents by Inventor Yong-suk Joo
Yong-suk Joo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11527273Abstract: A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.Type: GrantFiled: May 26, 2021Date of Patent: December 13, 2022Assignee: SK hynix Inc.Inventors: Kyung Ho Chu, Soo Bin Lim, Yong Suk Joo
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Publication number: 20210280227Abstract: A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.Type: ApplicationFiled: May 26, 2021Publication date: September 9, 2021Applicant: SK hynix Inc.Inventors: Kyung Ho CHU, Soo Bin LIM, Yong Suk JOO
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Patent number: 11049534Abstract: A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.Type: GrantFiled: March 4, 2020Date of Patent: June 29, 2021Assignee: SK hynix Inc.Inventors: Kyung Ho Chu, Soo Bin Lim, Yong Suk Joo
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Publication number: 20210074339Abstract: A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.Type: ApplicationFiled: March 4, 2020Publication date: March 11, 2021Applicant: SK hynix Inc.Inventors: Kyung Ho CHU, Soo Bin LIM, Yong Suk JOO
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Patent number: 10790038Abstract: A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.Type: GrantFiled: December 11, 2018Date of Patent: September 29, 2020Assignee: SK hynix Inc.Inventors: Soo Young Jang, Kyu Bong Kong, Geun Il Lee, Yong Suk Joo, Kyung Ho Chu
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Publication number: 20190385689Abstract: A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.Type: ApplicationFiled: December 11, 2018Publication date: December 19, 2019Applicant: SK hynix Inc.Inventors: Soo Young JANG, Kyu Bong KONG, Geun Il LEE, Yong Suk JOO, Kyung Ho CHU
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Publication number: 20170330634Abstract: A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. The semiconductor device may generate a plurality of control codes from the command/address signals in a test mode according to a combination of the command/address signals. The semiconductor device may output a first output datum generated by serializing the plurality of control codes, and the first output datum, through a single pad.Type: ApplicationFiled: August 3, 2017Publication date: November 16, 2017Applicant: SK hynix Inc.Inventors: Geun Ho CHOI, Yong Suk JOO
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Patent number: 9761328Abstract: A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. The semiconductor device may generate a plurality of control codes from the command/address signals in a test mode according to a combination of the command/address signals. The semiconductor device may output a first output datum generated by serializing the plurality of control codes, and the first output datum, through a single pad.Type: GrantFiled: October 8, 2015Date of Patent: September 12, 2017Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Yong Suk Joo
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Publication number: 20160351237Abstract: A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. The semiconductor device may generate a plurality of control codes from the command/address signals in a test mode according to a combination of the command/address signals. The semiconductor device may output a first output datum generated by serializing the plurality of control codes, and the first output datum, through a single pad.Type: ApplicationFiled: October 8, 2015Publication date: December 1, 2016Inventors: Geun Ho CHOI, Yong Suk JOO
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Patent number: 9129705Abstract: The semiconductor device includes an input clock generator and a data input unit. The input clock generator generates an input clock signal including a first pulse and a second pulse, wherein the first pulse is generated in response to a write signal and a write latency signal and the second pulse is generated in response to an external command signal and a burst length signal. The data input unit receives data and generates first input data in response to the first pulse of the input clock signal and receives the data and generates second input data in response of the second pulse of the input clock signal.Type: GrantFiled: April 11, 2014Date of Patent: September 8, 2015Assignee: SK Hynix Inc.Inventor: Yong Suk Joo
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Publication number: 20150146492Abstract: The semiconductor device includes an input clock generator and a data input unit. The input clock generator generates an input clock signal including a first pulse and a second pulse, wherein the first pulse is generated in response to a write signal and a write latency signal and the second pulse is generated in response to an external command signal and a burst length signal. The data input unit receives data and generates first input data in response to the first pulse of the input clock signal and receives the data and generates second input data in response of the second pulse of the input clock signal.Type: ApplicationFiled: April 11, 2014Publication date: May 28, 2015Applicant: SK hynix Inc.Inventor: Yong Suk JOO
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Publication number: 20140049310Abstract: A semiconductor device includes a plurality of oscillation signal generation units configured to output a plurality of oscillation signals whose cycles are adjusted according to a PN ratio, which is a size ratio of a PMOS transistor to an NMOS transistor, and a selection unit configured to selectively output the oscillation signals outputted from the plurality of oscillation signal generation units in response to a test mode signal.Type: ApplicationFiled: December 10, 2012Publication date: February 20, 2014Applicant: SK HYNIX INC.Inventors: Yong-Suk JOO, Joo-Hwan CHO
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Patent number: 7859939Abstract: A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequency of the second clock becomes identical to a frequency of the first clock, a phase comparison unit configured to compare a phase of the first clock with that of a clock outputted from the frequency conversion unit, and output a comparison signal corresponding to the comparison result, a logic level change unit configured to change a logic level of a training information signal when a logic level of the comparison signal is fixed for a given time after being changed, and a signal transfer unit configured to transfer the training information signal to the external.Type: GrantFiled: December 3, 2008Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventors: Yong-Suk Joo, Joo-Hwan Cho
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Patent number: 7672183Abstract: A semiconductor memory device includes: a pre-amplifying unit configured to amplify a difference between an input signal and a reference signal to output a pre-output signal; a delaying unit configured to delay the input signal to output a delayed input signal; and a main amplifying unit configured to receive the pre-output signal and the delayed input signal as differential inputs to output an output signal.Type: GrantFiled: December 11, 2007Date of Patent: March 2, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Yong-Suk Joo, Byoung-Jin Choi
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Publication number: 20100008177Abstract: A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequency of the second clock becomes identical to a frequency of the first clock, a phase comparison unit configured to compare a phase of the first clock with that of a clock outputted from the frequency conversion unit, and output a comparison signal corresponding to the comparison result, a logic level change unit configured to change a logic level of a training information signal when a logic level of the comparison signal is fixed for a given time after being changed, and a signal transfer unit configured to transfer the training information signal to the external.Type: ApplicationFiled: December 3, 2008Publication date: January 14, 2010Inventors: Yong-Suk Joo, Joo-Hwan Cho
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Patent number: 7606089Abstract: A data strobe signal generator includes a control unit, a pulse delay unit, a clock generator, and a data strobe output unit. The control unit generates a CAS latency signal and a preamble signal. The pulse delay unit delays a pulse signal for predetermined time and outputs a delayed pulse signal. The clock generator outputs a control clock signal. The data strobe output unit outputs a data strobe signal. The data strobe signal generator and the semiconductor memory device having the same generate a data strobe signal based on an adjustable preamble value, thereby ensuring the stabilized data output operation of a high-speed memory device.Type: GrantFiled: December 12, 2006Date of Patent: October 20, 2009Assignee: Hynix Semiconductor Inc.Inventor: Yong Suk Joo
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Patent number: 7495991Abstract: A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.Type: GrantFiled: December 4, 2007Date of Patent: February 24, 2009Assignee: Hynix Semiconductor Inc.Inventors: Geun-Il Lee, Yong-Suk Joo
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Publication number: 20080247250Abstract: A semiconductor memory device includes: a pre-amplifying unit configured to amplify a difference between an input signal and a reference signal to output a pre-output signal; a delaying unit configured to delay the input signal to output a delayed input signal; and a main amplifying unit configured to receive the pre-output signal and the delayed input signal as differential inputs to output an output signal.Type: ApplicationFiled: December 11, 2007Publication date: October 9, 2008Inventors: Yong-Suk Joo, Byoung-Jin CHOI
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Publication number: 20080159056Abstract: An internal address generation circuit in a semiconductor memory receives an external address signal and generates an internal address. The internal address generation circuit includes a control unit outputting at least more than two address strobe signals which are different from an internal command signal in terms of a strobe timing by decoding an external command signal; and an internal address generation unit outputting an internal address signal by aligning a first and a second address in a row by using the address strobe signal which are inputted sequentially, and there is an effect that an internal address is generated by using a plurality of address signals which are applied to one pad sequentially.Type: ApplicationFiled: July 18, 2007Publication date: July 3, 2008Inventors: Ki Chon PARK, Yong Suk JOO
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Publication number: 20080089107Abstract: A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.Type: ApplicationFiled: December 4, 2007Publication date: April 17, 2008Inventors: Geun-Il Lee, Yong-Suk Joo