Abstract: A pixel may include: an emission area and a non-emission area; a first bank in the non-emission area, the first bank including an opening corresponding to the emission area; a first electrode, a second electrode, and an intermediate electrode that are spaced from each other; light emitting elements in the emission area, each of the light emitting elements including one end portion electrically connected to one of the first electrode, the second electrode, or the intermediate electrode and an other end portion electrically connected to another one of the first electrode, the second electrode, or the intermediate electrode; and a sub-bank located in the opening of the first bank, the sub-bank being spaced from the first bank. The intermediate electrode may be around at least a portion of the sub-bank.

Abstract: A display device includes electrodes in an emission area of a pixel, and spaced apart from each other, light-emitting elements respectively between the electrodes, connection electrodes above the light-emitting elements, and including a first electrode portion, a second electrode portion, and a connection portion between the first electrode portion and the second electrode portion, and a shielding electrode in a non-emission area of the pixel, and overlapping the connection portion.

Abstract: A display device includes electrodes spaced apart from each other in a display area, an insulating layer disposed on the electrodes, light emitting elements disposed between the electrodes on the insulating layer, a signal line electrically connected to the light emitting elements, and a pad electrode electrically connected to the signal line, the pad electrode and the electrodes being disposed on a same layer in a non-display area. The insulating layer includes an opening exposing the pad electrode, and the signal line does not overlap the opening of the insulating layer in plan view.

Abstract: A display device includes a substrate including a display area and a pad area, a circuit element layer on the substrate, and an alignment electrode layer on the circuit element layer, wherein the circuit element layer includes a thin film transistor in the display area, and a pad electrode in the pad area, the alignment electrode layer includes a first alignment electrode and a second alignment electrode spaced from each other in the display area, and a pad upper electrode includes a first opening exposing the pad electrode in the pad area, and a light emitting element is on a space between the first alignment electrode and the second alignment electrode that are spaced from each other.

Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Abstract: A display device comprises a thin film transistor layer comprising a first metal layer disposed on a substrate and a thin film transistor disposed on the first metal layer, first and second electrodes disposed in a display area on the thin film transistor layer and extending in parallel in a direction, a plurality of light emitting elements disposed between the first and second electrodes, and an alignment line disposed in a non-display area disposed adjacent to the display area and electrically connected to the first and second electrodes. The alignment line comprises metal patterns disposed in the first metal layer and spaced apart from each other, and a bridge portion disposed on the first metal layer and electrically connected to the metal patterns.

Abstract: A display device includes a display area and a pad area. The display device may include a pixel on a base layer in the display area, the pixel including a light emitting element, and pads on the base layer in the pad area. The pads may include pad lines including first and second pad lines and first and second electrode parts. The pads may include a first contact area and a second contact area. The first pad line and the second pad line may be electrically connected to each other in the first contact area. The second pad line and the second electrode part may be electrically connected in the second contact area. The first electrode part may overlap the second pad line in a plan view. The first and second electrode parts may be electrically separated from each other by a pad insulating pattern.

Abstract: A display device includes a conductive pattern on a substrate, a via layer on the conductive pattern with a via hole exposing the conductive pattern, a first electrode and a second electrode on the via layer and spaced apart from each other, a first insulating layer on the first electrode and the second electrode, a bank layer on the first insulating layer defining an emission area and a subarea, a light-emitting element on the first insulating layer, and a first connection electrode and a second connection electrode on the first insulating layer and the light-emitting element. The first connection electrode electrically contacts an end of the light-emitting element, and the second connection electrode electrically contacts another end of the light-emitting element. The bank layer includes a bank extension portion extended to the subarea and the bank extension portion overlaps at least a portion of the via hole.

Abstract: A display device includes a substrate including a display area and a non-display area; pixels disposed in the display area and including respective light emitting units; a first conductive pattern disposed between the pixels; and a power source line disposed in the non-display area and electrically connected to the first conductive pattern. Each of the light emitting units includes a light emitting element, a first pixel electrode disposed on a first end of the light emitting element, and a second pixel electrode disposed on a second end of the light emitting element. The first conductive pattern and the second pixel electrode are disposed on a same layer.

Abstract: A display device includes a substrate, first and second bridge electrodes on the substrate and spaced apart from each other, a first electrode on the first bridge electrode, a second electrode on the second bridge electrode and spaced apart from the first electrode, a first insulating layer on the first electrode and the second electrode, a light emitting element on the first insulating layer, and on the first electrode and the second electrode, a first connection electrode on the first electrode, and contacting the light emitting element and the first bridge electrode, and a second connection electrode on the second electrode, and contacting the light emitting element and the second bridge electrode, wherein the first electrode directly contacts the first bridge electrode, and is separated from the first connection electrode, and wherein the second electrode directly contacts the second bridge electrode, and is separated from the second connection electrode.

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

Abstract: A display device includes a first electrode and a second electrode spaced apart from each other, each of the first electrode and the second electrode including an electrode base layer, a main electrode layer disposed on the electrode base layer, and an electrode upper layer disposed on a portion of the main electrode layer, a first insulating layer disposed on the first electrode and the second electrode, light-emitting elements disposed on the first electrode and the second electrode on the first insulating layer, a first connecting electrode electrically contacting the light-emitting elements, and a second connecting electrode electrically contacting the light-emitting elements. The first electrode includes a first part, the second electrode includes a second part, and the light-emitting elements are disposed on the first part and the second part.

Abstract: A display device includes: a first electrode and a second electrode that are spaced apart from each other; a light emitting element between the first electrode and the second electrode; a first connecting electrode contacting the first electrode and a first end of the light emitting element; a second connecting electrode contacting the second electrode and a second end of the light emitting element; a first insulating pattern between the first connecting electrode and the second connecting electrode above the light emitting element; and a second insulating pattern including first inorganic layers and second inorganic layers that are alternately stacked with each other between the first connecting electrode and the second connecting electrode above the first insulating pattern.

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

Abstract: A scan driver has a plurality of stages configured to supply a scan signal to scan lines. The plurality of stages include a stage coupled to a scan line of the scan lines. The stage includes a first transistor including a gate electrode, a drain electrode and a source electrode and is configured to output the scan signal to the scan line; a second transistor provided on a side of the first transistor and connected to the drain electrode; a third transistor provided on the side of the first transistor and connected to the source electrode; a capacitor provided between the scan line and the first transistor; a first dummy transistor provided between the first transistor and the capacitor and connected to the capacitor; and a second dummy transistor provided between the first transistor and the second transistor and connected to both the first transistor and the second transistor.

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

Abstract: A liquid crystal display device includes a display area, a peripheral area, and a boundary area between the display area and the peripheral area and further includes: a first substrate; a switching element disposed on the first substrate in the display area; a pad disposed on the first substrate in the peripheral area and electrically connected with the switching element; a protective film disposed on the first substrate in the display area, the peripheral area, and the boundary area, and covering the switching element and the pad; a color filter disposed on the protective film in the display area; and a planarization film covering the color filter and contacting the protective film in the boundary area and the peripheral area. The planarization film is provided with a first opening overlapping the pad and at least one second opening formed in the boundary area.