Patents by Inventor Yong Tae Cho

Yong Tae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7037778
    Abstract: Disclosed is a method for fabricating a capacitor in a semiconductor memory device. The method includes the steps of: sequentially forming a first insulation layer and a first etch stop layer on a substrate; forming a plurality of contact holes by etching the first insulation layer and the first etch stop layer; forming a plurality of contact plugs on the plurality of contact holes such that the contact plugs are more projected than the first etch stop layer; sequentially forming a second etch stop layer and a capacitor insulation layer; forming a plurality of openings by etching the second etch stop layer and the capacitor insulation layer to expose the contact plugs; sequentially forming a storage node material and a sacrificial layer; etching the storage node material and the sacrificial layer, thereby obtaining isolated storage node material; and removing remaining portions of the sacrificial layer and the capacitor insulation layer.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: May 2, 2006
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Yong-Tae Cho
  • Publication number: 20060003539
    Abstract: Disclosed is a method for fabricating a capacitor in a semiconductor memory device. The method includes the steps of: sequentially forming a first insulation layer and a first etch stop layer on a substrate; forming a plurality of contact holes by etching the first insulation layer and the first etch stop layer; forming a plurality of contact plugs on the plurality of contact holes such that the contact plugs are more projected than the first etch stop layer; sequentially forming a second etch stop layer and a capacitor insulation layer; forming a plurality of openings by etching the second etch stop layer and the capacitor insulation layer to expose the contact plugs; sequentially forming a storage node material and a sacrificial layer; etching the storage node material and the sacrificial layer, thereby obtaining isolated storage node material; and removing remaining portions of the sacrificial layer and the capacitor insulation layer.
    Type: Application
    Filed: December 20, 2004
    Publication date: January 5, 2006
    Applicant: Hynix Semiconductor Inc.
    Inventor: Yong-Tae Cho
  • Patent number: 6566188
    Abstract: A method of manufacturing a capacitor of a semiconductor device. In order to reduce a vertical etching profile at a lower portion of a hole where a charge storage electrode, an impurity is doped into the interlayer insulating film wherein the difference in concentration of the impurity at a lower portion and at an upper portion of the interlayer insulating film is controlled to make the etching rate at the lower portion of the interlayer insulating film faster than that at the upper portion of the interlayer insulating film using a wet etching process. Therefore, the region where a lower electrode will be formed has a maximum width to prevent a decrease in the capacitance of the capacitor.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: May 20, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Hyun Kim, Bong Ho Choi, Yong Tae Cho
  • Publication number: 20020197813
    Abstract: A method of manufacturing a capacitor of a semiconductor device. In order to reduce a vertical etching profile at a lower portion of a hole where a charge storage electrode, an impurity is doped into the interlayer insulating film wherein the difference in concentration of the impurity at a lower portion and at an upper portion of the interlayer insulating film is controlled to make the etching rate at the lower portion of the interlayer insulating film faster than that at the upper portion of the interlayer insulating film using a wet etching process. Therefore, the region where a lower electrode will be formed has a maximum width to prevent a decrease in the capacitance of the capacitor.
    Type: Application
    Filed: June 21, 2002
    Publication date: December 26, 2002
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Dong Hyun Kim, Bong Ho Choi, Yong Tae Cho
  • Patent number: 6276756
    Abstract: A height adjusting assembly for chairs. The assembly includes a first member having a taper holder positioned near an opening/closing pin and a taper arm engaged with the taper holder so as to push the opening/closing pin. A second member having a case, a lead arm engaged with the case and a button which operates the lead arm. A third member having a wire in which one end is connected to the taper arm and the other end is connected to the lead arm and a covering member in which one end is connected to the taper holder and the other end is connected to the case so that the wire is slidable in the covering member and the opening/closing pin is pushed by an operation of the taper arm which is engaged with the wire when the lead arm is operated by the button. The pushing force of the button can be controlled by the length of the taper arm and the rod arm. The height of a chair is adjusted easily and conveniently as the button is installed in the arm resting member of a chair.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: August 21, 2001
    Assignee: Samhongsa Co. Ltd.
    Inventors: Yong Tae Cho, Song Hur