Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.

Abstract: The present invention is about phased array antenna using gain switched multimode Fabry-Perot laser diode (FP-LD) and high-dispersion fiber. More particularly, the invention deals with techniques that allow compact and low-cost system implementation for phased array antenna adopting optical control and also allows continuous time delay for each antenna in the array to induce phase difference.

Abstract: A ferroelectric memory device and a method of fabricating the same are disclosed. Four interlayer dielectric layers are stacked on cell array and peripheral circuit regions on a semiconductor substrate. A gate contact pad and a source/drain contact pad are connected to a gate electrode and a source/drain of the peripheral circuit transistor through the first interlayer dielectric layer. A gate contact plug and a source/drain contact plug are respectively connected to the gate contact pad and the source/drain contact pad through the second interlayer dielectric layer. First via holes expose the gate contact plug and the source contact plug through the third interlayer dielectric layer. A first interconnection extends between the third and fourth interlayer dielectric layers, covering the sidewalls of the first via holes and connected to at least one of the gate contact plug and the source/drain contact plug.

Abstract: A method of fabricating a semiconductor device having a capacitor with a high dielectric constant layer includes a groove for an alignment key is formed together with a contact hole on a substrate; a conductive layer of tungsten is formed to fill the contact hole and cover the inner surface of the groove; a capping layer for use as an oxygen barrier is stacked on the conductive layer of tungsten; a planarization process is performed using CMP to leave the capping layer and the conductive layer of tungsten covering the inner surface of the groove to form a contact plug filling the contact hole; a capacitor bottom electrode layer is stacked to contact the top surface of the contact plug; a high dielectric constant layer is stacked on the bottom electrode layer; and an oxidation treatment is performed at a high temperature to crystallize the high dielectric constant layer.

Abstract: Disclosed is a wavelength stabilizing method in which a first QCSE photodetector and a second QCSE photodetector receive a light outputted from a single light source, a first wavelength-photocurrent graph obtained when a selected bias voltage is applied to the first QCSE photodetector and a second wavelength-photocurrent graph obtained when a selected bias voltage is applied to the first QCSE photodetector are overlapped at a predetermined reference wavelength, a photocurrent outputted from the first QCSE photodetector is greater than a photocurrent outputted from the second QCSE photodetector at wavelengths shorter than the overlapped point while the photocurrent outputted from the second QCSE photodetector is greater than the photocurrent outputted from the first QCSE photodetector at wavelengths longer than the overlapped point, and if the photocurrent outputted from the first QCSE photodetector is greater than the photocurrent output from the second QCSE photodetector, output wavelengths are moved to the

Abstract: A system for measuring chromatic dispersion in an optical fiber includes a multimode laser diode adapted to generate an optical pulse through gain switching; a highly dispersive optical fiber adapted to allow the optical output pulse to pass therethrough, and then adapted to separate each mode of the multimode laser diode to generate a reference signal; a test optical fiber adapted to allow an optical pulse for each wavelength separated by the highly dispersive optical fiber to pass therethrough to vary a repetition rate of the optical pulse train due to a chromatic dispersion characteristic of the test optical fiber using the optical pulse as the reference signal; and a high speed photodetector and RF spectrum analyzer adapted to detect eh variation of the repetition rate of the optical pulse train due to the chromatic dispersion characteristic of the test optical fiber.

Abstract: The present invention is about phased array antenna using gain switched multimode Fabry-Perot laser diode (FP-LD) and high-dispersion fiber. More particularly, the invention deals with techniques that allow compact and low-cost system implementation for phased array antenna adopting optical control and also allows continuous time delay for each antenna in the array to induce phase difference.

Abstract: In the ferroelectric memory device an auxiliary polysilicon layer is formed on an interlayer insulating layer having a polysilicon contact plug formed therein. A metal silicide layer is formed on the auxiliary polysilicon layer. A capacitor structure is then formed on the metal silicide layer.

Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern in performed.

Abstract: A ferroelectric memory device and a method of fabricating the same are disclosed. Four interlayer dielectric layers are stacked on cell array and peripheral circuit regions on a semiconductor substrate. A gate contact pad and a source/drain contact pad are connected to a gate electrode and a source/drain of the peripheral circuit transistor through the first interlayer dielectric layer. A gate contact plug and a source/drain contact plug are respectively connected to the gate contact pad and the source/drain contact pad through the second interlayer dielectric layer. First via holes expose the gate contact plug and the source contact plug through the third interlayer dielectric layer. A first interconnection extends between the third and fourth interlayer dielectric layers, covering the sidewalls of the first via holes and connected to at least one of the gate contact plug and the source/drain contact plug.

Abstract: A semiconductor memory device having a capacitor protection layer and a method for manufacturing the same. A capacitor of the semiconductor memory device is entirely covered with an encapsulating layer having a multi-layered structure. The encapsulating layer comprises at least a blocking layer and a capacitor protection layer, each of which is formed of different materials. The blocking is formed of a material capable of preventing a capacitor dielectric layer from volatilizing and/or capable of preventing a reaction between a material layer under the blocking layer and the capacitor protection layer. The capacitor protection layer is formed of a material layer capable of preventing diffusion of hydrogen into the capacitor dielectric layer. In addition, the semiconductor memory device may has a hydrogen barrier layer as another capacitor protection layer, between the capacitor and a passivation layer.

Abstract: A method of fabricating a semiconductor device having a capacitor with a high dielectric constant layer includes a groove for an alignment key is formed together with a contact hole on a substrate; a conductive layer of tungsten is formed to fill the contact hole and cover the inner surface of the groove; a capping layer for use as an oxygen barrier is stacked on the conductive layer of tungsten; a planarization process is performed using CMP to leave the capping layer and the conductive layer of tungsten covering the inner surface of the groove to form a contact plug filling the contact hole; a capacitor bottom electrode layer is stacked to contact the top surface of the contact plug; a high dielectric constant layer is stacked on the bottom electrode layer; and an oxidation treatment is performed at a high temperature to crystallize the high dielectric constant layer.

Abstract: A semiconductor device having a hydrogen diffusion barrier layer and a fabrication method thereof are provided. An ozone flushing treatment is performed before and/or after forming the hydrogen diffusion barrier layer. The hydrogen diffusion barrier layer can be formed of aluminum oxide or tantalum oxide. The ozone flushing treatment is preferably performed with an ozone concentration of about 100 to 300 g/m3 at a temperature of about 200 to 550° C. for approximately 1 to 10 minutes.

Abstract: Disclosed is a system for measuring a chromatic dispersion in an optical fiber, comprising: a multimode laser diode adapted to generate an optical pulse through a gain switching; a highly dispersive optical fiber adapted to allow the optical output pulse to pass therethrough, and then adapted to separate each mode of the multimode laser diode to generate a reference signal; a test optical fiber adapted to allow an optical pulse for each wavelength separated by the highly dispersive optical fiber to pass therethrough to vary a repetition rate of the optical pulse train due to a chromatic dispersion characteristic of the test optical fiber using the optical pulse as the reference signal; a high speed photodetector and a RF spectrum analyzer adapted to detect the variation of the repetitions rate of the optical pulse train due to the chromatic dispersion characteristic of the test optical fiber;

Abstract: A method for etching a metal layer of a semiconductor device is provided. A metal layer formed on a substrate is etched using a hard mask and a mixed etching gas containing chlorine and oxygen in which the ratio of oxygen gas is preferably about 0.5-0.8. Under such conditions, a metal layer pattern of a fine profile is formed. Since the hard mask is thin, it is possible to prevent etch reactants generated in a process of etching the metal layer from being deposited on the side surface of the resultant formed of the metal layer pattern and the hard mask. As a result, no additional processing is required to remove the etch reactants from the side surfaces and the metal layer etching process is simplified.

Abstract: A method of manufacturing a GaAs field effect transistor comprises depositing a silicon thin film 202 on a semi-insulating semiconductor substrate 201, forming a first sensitive film 203 by a photolithography to define channel areas and ion-implanting n-type dopants into the substrate to form an activation layer, removing the first sensitive film, forming a second sensitive film 203a on the silicon thin film by photolithography to define an ohmic contact area and then forming a highly doped impurity layer on the side of the activation layer by way of an ion-implantation process, depositing a passivation film 206 over the entire surface of the substrate 201 after the removal of the sensitive film, and effecting an annealing or heat treatment, forming a third sensitive film of a predetermined pattern by using an ohmic contact forming mask, effecting a recess etching process to the surface of the substrate and forming an ohmic contact on the etched portion, and patterning a gate region by using the gate forming

Abstract: The present invention relates to an integrated photoelectric receiving device in which a PIN-type photodetector and a junction field effect transistor (FET) are integrated in a single chip. The photoelectric receiving device comprises a photodetector having a n-channel layer, an etching stopper layer and an absorption layer formed on a semi-dielectric substrate, the n-channel layer, the etching stopper layer and the absorption layer being formed in a reverse mesa shape and the substrate being etched by a predetermined depth; a transistor having a n-channel layer, an etching stopper layer and a p-type InP layer sequentially formed on the non-etched portion of the semi-insulator substrate, the p-type InP layer having an absorption layer formed thereon in a reversedmesa shape. Also, the invention contemplates a method of manufacturing the device.